公开(公告)号：US20210320250A1

公开(公告)日：2021-10-14

申请号：US16844450

申请日：2020-04-09

Applicant: Infineon Technologies AG

Inventor： Dominik Heiss ,  Martin Bartels ,  Christoph Glacer ,  Christoph Kadow ,  Matthias Markert ,  Hans Taddiken ,  Hans-Dieter Wohlmuth

IPC: H01L45/00

Abstract: A switching device includes first and second RF terminals disposed over a substrate, one or more strips of phase change material connected between the first and second RF terminals, a region of thermally insulating material that separates the one or more strips of phase change material from the substrate, and a heater structure comprising one or more heating elements that are configured to control a conductive connection between the first and second RF terminals by applying heat to the one or more strips of phase change material. Each of the one or more strips of phase change material includes a first outer face and a second outer face opposite from the first outer face. For each of the one or more strips of phase change material, at least portions of both of the first and second outer faces are disposed against one of the heating elements.

公开(公告)号：US20190043716A1

公开(公告)日：2019-02-07

申请号：US16043365

申请日：2018-07-24

Applicant: Infineon Technologies AG

Inventor： Christoph Kadow ,  Uwe Seidel

IPC: H01L21/02 ,  H01L25/065 ,  H01L21/268

Abstract: A method for manufacturing a device includes: providing a semiconductor substrate having an RF-device; providing a BEOL-layer stack on the first main surface of the semiconductor substrate; attaching a carrier structure to a first main surface of the BEOL-layer stack; removing a lateral portion of the semiconductor substrate which laterally adjoins the device region to expose a lateral portion of the second main surface of the BEOL-layer stack; and opening a contacting region of the BEOL-layer stack at the lateral portion of second main surface of the BEOL-layer stack.

公开(公告)号：US09865792B2

公开(公告)日：2018-01-09

申请号：US14282886

申请日：2014-05-20

Applicant: Infineon Technologies AG

Inventor： Donald Dibra ,  Christoph Kadow ,  Markus Zundel

IPC: G01K7/04 ,  H01L35/32 ,  G01K1/08 ,  G01K7/02

CPC classification number: H01L35/32 ,  G01K1/08 ,  G01K7/02

Abstract: An embodiment of the invention relates to a Seebeck temperature difference sensor that may be formed in a trench on a semiconductor device. A portion of the sensor may be substantially surrounded by an electrically conductive shield. A plurality of junctions may be included to provide a higher Seebeck sensor voltage. The shield may be electrically coupled to a local potential, or left electrically floating. A portion of the shield may be formed as a doped well in the semiconductor substrate on which the semiconductor device is formed, or as a metal layer substantially covering the sensor. The shield may be formed as a first oxide layer on a sensor trench wall with a conductive shield formed on the first oxide layer, and a second oxide layer formed on the conductive shield. An absolute temperature sensor may be coupled in series with the Seebeck temperature difference sensor.

公开(公告)号：US09761665B2

公开(公告)日：2017-09-12

申请号：US15157448

申请日：2016-05-18

Applicant: Infineon Technologies AG

Inventor： Thorsten Meyer ,  Stefan Decker ,  Norbert Krischke ,  Christoph Kadow

IPC: H01L27/148 ,  H01L29/768 ,  H01L29/10 ,  H01L21/265 ,  H01L21/266 ,  H01L21/8238 ,  H01L27/088 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8234 ,  H01L29/423

CPC classification number: H01L29/105 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/823412 ,  H01L21/823807 ,  H01L27/088 ,  H01L29/4236 ,  H01L29/66537 ,  H01L29/78

Abstract: An integrated circuit having field effect transistors and manufacturing method. One embodiment provides an integrated circuit including a first FET and a second FET. At least one of source, drain, gate of the first FET is electrically connected to the corresponding one of source, drain, gate of the second FET. At least one further of source, drain, gate of the first FET and the corresponding one further of source, drain, gate of the second FET are connected to a circuit element, respectively. A dopant concentration of a body along a channel of each of the first and second FETs has a peak at a peak location within the channel.

公开(公告)号：US20150364524A1

公开(公告)日：2015-12-17

申请号：US14303654

申请日：2014-06-13

Applicant: Infineon Technologies AG

Inventor： Christoph Kadow ,  Marc Strasser

IPC: H01L27/16 ,  H01L21/768 ,  G01K7/01 ,  H01L23/522

CPC classification number: H01L27/16 ,  G01K1/026 ,  G01K7/01 ,  G01K2217/00 ,  H01L21/76895 ,  H01L29/0653 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/7393 ,  H01L29/7826

Abstract: A power semiconductor device includes a semiconductor body including a first surface, an edge delimiting the semiconductor body in a horizontal direction substantially parallel to the first surface, an active area including at least one of several transistor structures connected in parallel and several diode structures connected in parallel, and a peripheral area arranged between the active area and the edge. The power semiconductor further device includes a plurality of word lines, a plurality of bit lines separated from the word lines, and a plurality of temperature sensors arranged on or at the first surface, wherein each of the temperature sensors is connected with one of the bit lines and one of the word lines or each of the temperature sensors is formed by a respective portion of one of the bit lines.

Abstract translation: 功率半导体器件包括半导体本体，其包括第一表面，在基本上平行于第一表面的水平方向上限定半导体本体的边缘;有源区，包括并联连接的多个晶体管结构中的至少一个，以及连接在 平行和布置在有效区域和边缘之间的周边区域。 功率半导体另外的器件包括多个字线，与字线分离的多个位线，以及布置在第一表面上或第一表面上的多个温度传感器，其中每个温度传感器与位中的一个连接 线和一条字线或每个温度传感器由位线之一的相应部分形成。

公开(公告)号：US20150214357A1

公开(公告)日：2015-07-30

申请号：US14682755

申请日：2015-04-09

Applicant: Infineon Technologies AG

Inventor： Andreas Peter Meiser ,  Markus Zundel ,  Christoph Kadow

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/739

CPC classification number: H01L29/7813 ,  H01L21/823487 ,  H01L27/088 ,  H01L29/0653 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/41775 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/42372 ,  H01L29/4238 ,  H01L29/42392 ,  H01L29/66666 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/7827

Abstract: A vertical transistor component includes a semiconductor body with first and second surfaces, a drift region, and a source region and body region arranged between the drift region and the first surface. The body region is also arranged between the source region and the drift region. The vertical transistor component further includes a gate electrode arranged adjacent to the body zone, a gate dielectric arranged between the gate electrode and the body region, and a drain region arranged between the drift region and the second surface. A source electrode electrically contacts the source region, is electrically insulated from the gate electrode and arranged on the first surface. A drain electrode electrically contacts the drain region and is arranged on the second surface. A gate contact electrode is electrically insulated from the semiconductor body, extends in the semiconductor body to the second surface, and is electrically connected with the gate electrode.

Abstract translation: 垂直晶体管组件包括具有第一和第二表面的半导体本体，漂移区以及布置在漂移区和第一表面之间的源区和体区。 身体区域也布置在源区域和漂移区域之间。 垂直晶体管部件还包括邻近体区设置的栅极电极，布置在栅极电极和主体区域之间的栅极电介质，以及布置在漂移区域和第二表面之间的漏极区域。 源电极与源区电接触，与栅电极电绝缘并且布置在第一表面上。 漏电极与漏极区域电接触并设置在第二表面上。 栅极接触电极与半导体本体电绝缘，在半导体本体中延伸到第二表面，并与栅电极电连接。

公开(公告)号：US20130307062A1

公开(公告)日：2013-11-21

申请号：US13949968

申请日：2013-07-24

Applicant: Infineon Technologies AG

Inventor： Andreas Peter Meiser ,  Markus Zundel ,  Christoph Kadow

IPC: H01L29/78

CPC classification number: H01L29/7813 ,  H01L21/823487 ,  H01L27/088 ,  H01L29/0653 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/41775 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/42372 ,  H01L29/4238 ,  H01L29/42392 ,  H01L29/66666 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/7827

Abstract: A vertical transistor component includes a semiconductor body with first and second surfaces, a drift region, and a source region and body region arranged between the drift region and the first surface. The body region is also arranged between the source region and the drift region. The vertical transistor component further includes a gate electrode arranged adjacent to the body zone, a gate dielectric arranged between the gate electrode and the body region, and a drain region arranged between the drift region and the second surface. A source electrode electrically contacts the source region, is electrically insulated from the gate electrode and arranged on the first surface. A drain electrode electrically contacts the drain region and is arranged on the second surface. A gate contact electrode is electrically insulated from the semiconductor body, extends in the semiconductor body to the second surface, and is electrically connected with the gate electrode.