公开(公告)号：US20220179797A1

公开(公告)日：2022-06-09

申请号：US17682111

申请日：2022-02-28

Applicant: Intel Corporation

Inventor： Jeffrey C. Swanson ,  Sreenivas Mandava ,  Henk Neefs ,  Jing Ling

IPC: G06F12/0888 ,  G06F12/1018 ,  G06F9/46 ,  G06F9/48

Abstract: An embodiment of an apparatus may comprise one or more substrates, and a controller coupled to the one or more substrates, the controller including circuitry to control access to a memory, convert an address for a transaction for the memory from a first address in a first address space to a second address in a second address space, determine a bandwidth bypass condition for the transaction based on a bandwidth of memory transactions for the memory, and provide the second address for the transaction to a scheduler at a time based at least in part on the determined bandwidth bypass condition. Other embodiments are disclosed and claimed.

公开(公告)号：US09626321B2

公开(公告)日：2017-04-18

申请号：US14060191

申请日：2013-10-22

Applicant: Intel Corporation

Inventor： Robert J. Safranek ,  Robert G. Blankenship ,  Venkatraman Iyer ,  Jeff Willey ,  Robert Beers ,  Darren S. Jue ,  Arvind A. Kumar ,  Debendra Das Sharma ,  Jeffrey C. Swanson ,  Bahaa Fahim ,  Vedaraman Geetha ,  Aaron T. Spink ,  Fulvio Spagna ,  Rahul R. Shah ,  Sitaraman V. Iyer ,  William Harry Nale ,  Abhishek Das ,  Simon P. Johnson ,  Yuvraj S. Dhillon ,  Yen-Cheng Liu ,  Raj K. Ramanujan ,  Robert A. Maddox ,  Herbert H. Hum ,  Ashish Gupta

IPC: G06F13/40 ,  G06F12/0831 ,  G06F13/42 ,  G06F9/30 ,  G06F12/0806 ,  H04L12/933 ,  G06F9/46 ,  G06F12/0813 ,  G06F12/0815 ,  H04L12/741 ,  G06F9/44

CPC classification number: G06F13/22 ,  G06F1/3287 ,  G06F8/71 ,  G06F8/73 ,  G06F8/77 ,  G06F9/30145 ,  G06F9/44505 ,  G06F9/466 ,  G06F11/1004 ,  G06F12/0806 ,  G06F12/0808 ,  G06F12/0813 ,  G06F12/0815 ,  G06F12/0831 ,  G06F12/0833 ,  G06F13/4022 ,  G06F13/4068 ,  G06F13/4221 ,  G06F13/4282 ,  G06F13/4286 ,  G06F13/4291 ,  G06F2212/1016 ,  G06F2212/2542 ,  G06F2212/622 ,  H04L9/0662 ,  H04L12/4641 ,  H04L45/74 ,  H04L49/15 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151 ,  Y02D10/40 ,  Y02D10/44 ,  Y02D30/30

Abstract: A physical layer (PHY) is coupled to a serial, differential link that is to include a number of lanes. The PHY includes a transmitter and a receiver to be coupled to each lane of the number of lanes. The transmitter coupled to each lane is configured to embed a clock with data to be transmitted over the lane, and the PHY periodically issues a blocking link state (BLS) request to cause an agent to enter a BLS to hold off link layer flit transmission for a duration. The PHY utilizes the serial, differential link during the duration for a PHY associated task selected from a group including an in-band reset, an entry into low power state, and an entry into partial width state

公开(公告)号：US09537665B2

公开(公告)日：2017-01-03

申请号：US13971729

申请日：2013-08-20

Applicant: Intel Corporation

Inventor： Selim Bilgin ,  Lily P. Looi ,  Jeffrey C. Swanson

IPC: G06F1/32 ,  H04L12/12 ,  H04L12/10

CPC classification number: H04L12/12 ,  G06F1/3203 ,  H04L12/10

Abstract: To address the need for power management, the following facilitates maintaining power states in an efficient manner based at least in part on managing packets at different layers of an input/output interface that supports multiple layers. One specific example prevents a destructive event for link layer control logic because packets and information might have been lost or dropped due to a hang condition and/or a dropped packet. In yet another example of power management, this facilitates a low power platform state by preventing the loss of packets or data upon exiting a platform power state upon initiation of a link reset condition by preventing certain types of packets from reaching link layer controller logic.

Abstract translation: 为了解决对电力管理的需要，以下有助于以至少部分地基于在支持多层的输入/输出接口的不同层处理分组的方式以有效的方式维持功率状态。 一个具体示例防止链路层控制逻辑的破坏性事件，因为由于挂起条件和/或丢弃的分组，分组和信息可能已经丢失或丢弃。 在功率管理的另一示例中，这通过防止在启动链路复位条件时通过防止某些类型的分组到达链路层控制器逻辑而退出平台功率状态时丢失分组或数据来促进低功率平台状态。

公开(公告)号：US09479196B2

公开(公告)日：2016-10-25

申请号：US13976947

申请日：2013-03-28

Applicant: Intel Corporation

Inventor： Jeff Willey ,  Robert G. Blankenship ,  Jeffrey C. Swanson ,  Robert J. Safranek

IPC: H03M13/09 ,  H03M13/00 ,  G06F13/42 ,  G06F13/00 ,  H04L12/46

CPC classification number: G06F11/1004 ,  G06F13/4221 ,  G06F13/4282 ,  G06F2213/0026 ,  H03M13/09 ,  H04L12/4641

Abstract: Transaction data is identified and a flit is generated to include three or more slots and a floating field to be used as an extension of any one of two or more of the slots. In another aspect, the flit is to include two or more slots, a payload, and a cyclic redundancy check (CRC) field to be encoded with a 16-bit CRC value generated based on the payload. The flit is sent over a serial data link to a device for processing, based at least in part on the three or more slots.

Abstract translation: 识别事务数据，并且生成飞行以包括三个或更多个时隙和要用作两个或更多个时隙中的任何一个的扩展的浮动字段。 在另一个方面，该方案包括要使用基于有效载荷生成的16位CRC值来编码的两个或更多个时隙，有效载荷和循环冗余校验（CRC）字段。 至少部分地基于三个或更多个时隙，将闪存通过串行数据链路发送到用于处理的设备。

公开(公告)号：US20160188500A1

公开(公告)日：2016-06-30

申请号：US14583147

申请日：2014-12-25

Applicant: Intel Corporation

Inventor： Brian S. Morris ,  Jeffrey C. Swanson ,  Bill Nale ,  Robert G. Blankenship ,  Jeff Willey ,  Eric L. Hendrickson

IPC: G06F13/16 ,  G11C7/10

CPC classification number: G06F13/1663 ,  G06F13/1673 ,  G11C5/04 ,  G11C7/10

Abstract: A plurality of completed writes to memory are identified corresponding to a plurality of write requests from a host device received over a buffered memory interface. A completion packet is sent to the host device that includes a plurality of write completions to correspond to the plurality of completed writes.

Abstract translation: 对存储器的多个完成的写入被识别为与通过缓冲存储器接口接收的主机设备的多个写入请求相对应。 完成分组被发送到主机设备，其包括多个写入完成以对应于多个完成的写入。

公开(公告)号：US09355058B2

公开(公告)日：2016-05-31

申请号：US13976937

申请日：2013-03-27

Applicant: Intel Corporation

Inventor： Venkatraman Iyer ,  Darren S. Jue ,  Robert G. Blankenship ,  Fulvio Spagna ,  Debendra Das Sharma ,  Jeffrey C. Swanson

IPC: G06F13/42 ,  G06N99/00

CPC classification number: G06F13/4291 ,  G06F1/24 ,  G06F1/3287 ,  G06F13/1678 ,  G06F13/42 ,  G06F13/4282 ,  G06N99/005

Abstract: A periodic control window is embedded in a link layer data stream to be sent over a serial data link, where the control window is configured to provide physical layer information including information for use in initiating state transitions on the data link. The link layer data can be sent during a link transmitting state of the data link and the control window can interrupt the sending of flits. In one aspect, the information includes link width transition data indicating an attempt to change the number of active lanes on the link.

公开(公告)号：US20150186327A1

公开(公告)日：2015-07-02

申请号：US14583554

申请日：2014-12-26

Applicant: Intel Corporation

Inventor： Jeff Willey ,  Robert G. Blankenship ,  Jeffrey C. Swanson

IPC: G06F13/42 ,  H03M13/09

CPC classification number: G06F13/4221 ,  G06F13/4265 ,  H03M13/09

Abstract: A link layer control message is generated and included in a flit that is to be sent over a serial data link to a device. The flits sent over the data link are to include a plurality of slots. Control messages can include, in some aspects, a viral alert message, a poison alert message, a credit return message, and acknowledgements.

Abstract translation: 生成链路层控制消息并将其包含在要通过串行数据链路发送到设备的飞行中。 通过数据链路发送的闪烁将包括多个时隙。 在一些方面，控制消息可以包括病毒警报消息，毒药警报消息，信用返回消息和确认。