公开(公告)号：US20240222435A1

公开(公告)日：2024-07-04

申请号：US18089936

申请日：2022-12-28

Applicant: Intel Corporation

Inventor： Abhishek Anil SHARMA ,  Han Wui THEN ,  Wilfred GOMES ,  Anand S. MURTHY ,  Tahir GHANI ,  Sagar SUTHRAM ,  Pushkar RANADE

IPC: H01L29/16 ,  H01L21/02 ,  H01L27/105

CPC classification number: H01L29/1608 ,  H01L21/02447 ,  H01L21/02529 ,  H01L27/105

Abstract: Embodiments described herein may be related to apparatuses, processes, systems, and/or techniques for fabricating semiconductor packages that use a SiC layer that is coupled with another layer that includes another material. The SiC layer may be an active layer that includes devices, such as transistors, that are coupled with devices that may be in the other layer. The SiC layer may be coupled with the other layer using fusion bonding, hybrid bonding, layer transfer, and/or bump and island formation techniques. Other embodiments may be described and/or claimed.

公开(公告)号：US20240215256A1

公开(公告)日：2024-06-27

申请号：US18088552

申请日：2022-12-24

Applicant: Intel Corporation

Inventor： Abhishek Anil SHARMA ,  Tahir GHANI ,  Anand S. MURTHY ,  Wilfred GOMES ,  Pushkar RANADE ,  Sagar SUTHRAM

IPC: H10B53/20 ,  H01L23/522 ,  H01L23/528 ,  H10B53/10 ,  H10B61/00

CPC classification number: H10B53/20 ,  H01L23/5226 ,  H01L23/5283 ,  H10B53/10 ,  H10B61/10 ,  H10B61/22

Abstract: Structures having backside capacitors are described. In an example, an integrated circuit structure includes a front side structure including a device layer having a plurality of select transistors, a plurality of metallization layers above the plurality of select transistors, and a plurality of vias below and coupled to the plurality of select transistors. A backside structure is below the plurality of vias of the device layer. The backside structure includes a memory layer coupled to the plurality of select transistors by the plurality of vias.

公开(公告)号：US20240215222A1

公开(公告)日：2024-06-27

申请号：US18088543

申请日：2022-12-24

Applicant: Intel Corporation

Inventor： Abhishek Anil SHARMA ,  Tahir GHANI ,  Sagar SUTHRAM ,  Anand S. MURTHY ,  Pushkar RANADE ,  Wilfred GOMES

IPC: H10B12/00

CPC classification number: H10B12/315

Abstract: Structures having backside power delivery and signal routing for front side DRAM are described. In an example, an integrated circuit structure includes a front side structure including a dynamic random access memory (DRAM) layer having one or more capacitors over one or more transistors, and a plurality of metallization layers above the DRAM layer. A backside structure is below and coupled to the transistors of the DRAM layer, the backside structure including metal lines for power delivery and signal routing to the one or more transistors of the DRAM layer.

公开(公告)号：US20240008253A1

公开(公告)日：2024-01-04

申请号：US17855545

申请日：2022-06-30

Applicant: Intel Corporation

Inventor： Abhishek Anil SHARMA ,  Tahir GHANI ,  Anand S. MURTHY ,  Wilfred GOMES ,  Cory WEBER ,  Rishabh MEHANDRU ,  Sagar SUTHRAM ,  Pushkar RANADE

IPC: H01L27/108

CPC classification number: H01L27/10814 ,  H01L27/10826

Abstract: Structures having memory access transistors with backside contacts are described. In an example, an integrated circuit structure includes a front-side structure including a device layer having a fin-based transistor, and a capacitor structure above the fin-based transistor of the device layer. A backside structure is below the front-side structure. The backside structure includes a conductive contact electrically connected to the fin-based transistor of the device layer.

公开(公告)号：US20240006531A1

公开(公告)日：2024-01-04

申请号：US17855573

申请日：2022-06-30

Applicant: Intel Corporation

Inventor： Abhishek Anil SHARMA ,  Rishabh MEHANDRU ,  Sagar SUTHRAM ,  Cory WEBER ,  Tahir GHANI ,  Anand S. MURTHY ,  Pushkar RANADE ,  Wilfred GOMES

IPC: H01L29/78 ,  H01L27/13 ,  H01L27/12 ,  H01L29/66

CPC classification number: H01L29/7827 ,  H01L27/13 ,  H01L27/124 ,  H01L29/66666

Abstract: Structures having vertical transistors are described. In an example, an integrated circuit structure includes a channel structure on a drain contact layer, the channel structure having an opening extending there through. A gate dielectric layer is on a bottom and along sides of the opening, the gate dielectric layer laterally surrounded by the channel structure. A gate electrode is on and laterally surrounded by the gate dielectric layer. A source contact layer is on sides of a portion of the gate dielectric layer extending above the channel structure.

公开(公告)号：US20240006317A1

公开(公告)日：2024-01-04

申请号：US17855586

申请日：2022-06-30

Applicant: Intel Corporation

Inventor： Abhishek Anil SHARMA ,  Tahir GHANI ,  Anand S. MURTHY ,  Cory WEBER ,  Rishabh MEHANDRU ,  Wilfred GOMES ,  Sagar SUTHRAM

IPC: H01L23/528 ,  H01L23/535 ,  H01L21/8238 ,  H01L21/768 ,  H01L27/092 ,  H01L29/78

CPC classification number: H01L23/5286 ,  H01L23/535 ,  H01L29/785 ,  H01L21/76898 ,  H01L27/0924 ,  H01L21/823871

Abstract: Structures having vertical keeper or power gate for backside power delivery are described. In an example, an integrated circuit structure includes a front-side structure including a device layer having a plurality of fin-based transistors, and a plurality of metallization layers above the fin-based transistors of the device layer. A backside structure is below the fin-based transistors of the device layer. The backside structure includes a ground metal line. One or more vertical gate all-around transistors is between the fin-based transistors of the device layer and the ground metal line of the backside structure.

公开(公告)号：US20210074695A1

公开(公告)日：2021-03-11

申请号：US16646460

申请日：2017-12-28

Applicant: Intel Corporation

Inventor： Wilfred GOMES ,  Mark BOHR ,  Glenn J. HINTON ,  Rajesh KUMAR

IPC: H01L25/18 ,  H01L23/538 ,  H01L23/48 ,  H01L25/065 ,  H01L23/00

Abstract: Techniques and mechanisms for providing interconnected circuitry of an integrated circuit (IC) die stack. In an embodiment, first integrated circuitry of a first IC die is configured to couple, via a first interconnects of the first IC die, to second integrated circuitry of a second IC die. When the first IC die and the second IC die are coupled to one another, second interconnects of the first IC die are further coupled to the second integrated circuitry, wherein the second interconnects are coupled to each of two opposite sides of the first IC die. In another embodiment, the second integrated circuitry includes processor logic, and the first integrated circuitry is configured to cache data for access by the processor logic. In another embodiment, the first integrated circuitry includes a power delivery circuit and an on-package input-output interface to cache data for access by the processor logic at higher bandwidth with lower power consumption.

公开(公告)号：US20240038722A1

公开(公告)日：2024-02-01

申请号：US18378978

申请日：2023-10-11

Applicant: Intel Corporation

Inventor： Mark T. BOHR ,  Wilfred GOMES ,  Rajesh KUMAR ,  Pooya TADAYON ,  Doug INGERLY

IPC: H01L25/065 ,  H01L23/522 ,  H01L23/538 ,  H01L23/00

CPC classification number: H01L25/0655 ,  H01L23/5226 ,  H01L23/5384 ,  H01L24/13 ,  H01L2225/06541

Abstract: Hyperchip structures and methods of fabricating hyperchips are described. In an example, an integrated circuit assembly includes a first integrated circuit chip having a device side opposite a backside. The device side includes a plurality of transistor devices and a plurality of device side contact points. The backside includes a plurality of backside contacts. A second integrated circuit chip includes a device side having a plurality of device contact points thereon. The second integrated circuit chip is on the first integrated circuit chip in a device side to device side configuration. Ones of the plurality of device contact points of the second integrated circuit chip are coupled to ones of the plurality of device contact points of the first integrated circuit chip. The second integrated circuit chip is smaller than the first integrated circuit chip from a plan view perspective.

公开(公告)号：US20240006483A1

公开(公告)日：2024-01-04

申请号：US17855567

申请日：2022-06-30

Applicant: Intel Corporation

Inventor： Abhishek Anil SHARMA ,  Tahir GHANI ,  Rishabh MEHANDRU ,  Anand S. MURTHY ,  Wilfred GOMES ,  Cory WEBER ,  Sagar SUTHRAM

IPC: H01L29/06 ,  H01L29/786 ,  H01L27/088 ,  H01L29/417 ,  H01L29/78

CPC classification number: H01L29/0673 ,  H01L29/78618 ,  H01L29/78696 ,  H01L27/0886 ,  H01L29/41791 ,  H01L29/7851

Abstract: Structures having raised epitaxy on channel structure transistors are described. In an example, an integrated circuit structure includes a channel structure having multi-layer epitaxial source or drain structures thereon, the multi-layer epitaxial source or drain structures having a recess extending there through. A gate dielectric layer is on a bottom and along sides of the recess and laterally surrounded by the epitaxial source or drain structures. A gate electrode is on and laterally surrounded by the gate dielectric layer. The gate electrode has an uppermost surface below an uppermost surface of the gate dielectric layer.

公开(公告)号：US20230422462A1

公开(公告)日：2023-12-28

申请号：US17851979

申请日：2022-06-28

Applicant: Intel Corporation

Inventor： Abhishek Anil SHARMA ,  Wilfred GOMES

IPC: H01L27/11 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L29/775

CPC classification number: H01L27/1108 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/78618 ,  H01L29/78696 ,  H01L29/775

Abstract: Structures having inverters with contacts between nanowires are described. In an example, an integrated circuit structure includes a stack of horizontal nanowires along a vertical direction. A conductive contact is laterally adjacent to a source or drain region of the stack of horizontal nanowires, the conductive contact having a cut in the vertical direction. A gate stack is over the stack of horizontal nanowires and surrounding a channel region of each of the horizontal nanowires, the gate stack laterally spaced apart from the conductive contact.