公开(公告)号：US20050161711A1

公开(公告)日：2005-07-28

申请号：US11065816

申请日：2005-02-25

申请人： Jack Oon Chu

发明人： Jack Oon Chu

IPC分类号： H01L21/02 ,  H01L21/28 ,  H01L21/336 ,  H01L27/12 ,  H01L29/10 ,  H01L29/417 ,  H01L29/423 ,  H01L29/49 ,  H01L29/778 ,  H01L29/78 ,  H01L29/786 ,  H01L29/04 ,  H01L31/036

CPC分类号： H01L29/785 ,  H01L21/2807 ,  H01L21/28255 ,  H01L29/1029 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/41783 ,  H01L29/42384 ,  H01L29/42392 ,  H01L29/4908 ,  H01L29/4966 ,  H01L29/66628 ,  H01L29/66795 ,  H01L29/778 ,  H01L29/7787 ,  H01L29/7842 ,  H01L29/78642 ,  H01L29/78648 ,  H01L29/78684 ,  H01L29/78696

摘要： Structure and methods of fabrication are disclosed for an enhanced FET devices in which dopant impurities are prevented from diffusing through the gate insulator. The structure comprises a Si:C, or SiGe:C, layer which is sandwiched between the gate insulator and a layer which is doped with impurities in order to provide a preselected workfunction. It is further disclosed how this, and further improvements for FET devices, such as raised source/drain and multifaceted gate on insulator, MODFET on insulator are integrated with strained Si based layer on insulator technology.

摘要翻译： 公开了用于增强的FET器件的制造结构和方法，其中防止掺杂剂杂质通过栅极绝缘体扩散。 该结构包括夹在栅极绝缘体和掺杂有杂质的层之间的Si：C或SiGe：C层，以提供预选的功函数。 还进一步公开了如何以及对FET器件的进一步改进，诸如凸起源极/漏极和绝缘体上的多面绝缘体，绝缘体上的MODFET与应变的基于Si的绝缘体上的技术集成。

公开(公告)号：US06723621B1

公开(公告)日：2004-04-20

申请号：US08885611

申请日：1997-06-30

申请人： Frank Cardone ,  Jack Oon Chu ,  Khalid EzzEldin Ismail

发明人： Frank Cardone ,  Jack Oon Chu ,  Khalid EzzEldin Ismail

IPC分类号： H01L2120

CPC分类号： H01L29/36 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/0262 ,  H01L21/26506 ,  H01L29/1054 ,  H01L29/41783 ,  H01L29/66431 ,  H01L29/66477 ,  H01L29/665 ,  H01L29/66575 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/7833

摘要： A structure and method of forming an abrupt doping profile is described incorporating a substrate, a first epitaxial layer of Ge less than the critical thickness having a P or As concentration greater than 5×1019 atoms/cc, and a second epitaxial layer having a change in concentration in its first 40 Å from the first layer of greater than 1×1019 P atoms/cc. Alternatively, a layer of SiGe having a Ge content greater than 0.5 may be selectively amorphized and recrystalized with respect to other layers in a layered structure. The invention overcomes the problem of forming abrupt phosphorus profiles in Si and SiGe layers or films in semiconductor structures such as CMOS, MODFET's, and HBT's.

摘要翻译： 描述了形成突变掺杂分布的结构和方法，其结合基片，Ge的第一外延层Ge小于P或As浓度大于5×10 19原子/ cc的临界厚度，以及第二外延层，其具有 从第一层大于1×10 19 P原子/ cc的第一层的浓度变化。 或者，具有Ge含量大于0.5的SiGe层可以相对于分层结构中的其它层选择性地非晶化并重结晶。 本发明克服了在诸如CMOS，MODFET和HBT等半导体结构中的Si和SiGe层或膜中形成突变磷分布的问题。

公开(公告)号：US06425951B1

公开(公告)日：2002-07-30

申请号：US09369995

申请日：1999-08-06

申请人： Jack Oon Chu ,  Khalid Ezzeldin Ismail

发明人： Jack Oon Chu ,  Khalid Ezzeldin Ismail

IPC分类号： C30B3306

CPC分类号： C23C16/54 ,  C23C16/0209 ,  C23C16/0227 ,  C23C16/24 ,  C30B25/02 ,  C30B25/08 ,  Y10S414/138 ,  Y10S414/139

摘要： An apparatus for forming a portion of an electronic device is described incorporating an Ultra High Vacuum-Chemical Vapor Deposition (UHV-CVD) system, a Low Pressure-Chemical Vapor Deposition (LP-CVD) system, and an Ultra High Vacuum (UHV) transfer system. A method for passivating a semiconductor substrate is described incorporating growing silicon containing layers, flowing a hydrogen containing gas and lowering the substrate temperature below 400° C. A method for removing native oxide is described. A method for growing a continuous epitaxial layer while performing a deposition interrupt is described. A method for forming a Si/Si oxide interface is described having low interface trap density. A method for forming a Si/Si oxide/p++ polysilicon gate stack. The invention overcomes the problem of requiring silicon containing wafers being dipped in HF acid prior to CVD processing. The invention overcomes the problem of surface passivation between in-situ processes in multiple CVD reactors.

摘要翻译： 描述了一种用于形成电子器件的一部分的装置，其包括超高真空 - 化学气相沉积（UHV-CVD）系统，低压 - 化学气相沉积（LP-CVD）系统和超高真空（UHV） 传输系统。 描述了一种用于钝化半导体衬底的方法，其包括生长含硅层，使含氢气体流动并将衬底温度降低到400℃以下。描述了去除天然氧化物的方法。 描述了一种在执行沉积中断时生长连续外延层的方法。 描述了形成Si / Si氧化物界面的方法具有低界面陷阱密度。 一种形成Si / Si氧化物/ p ++多晶硅栅叠层的方法。 本发明克服了在CVD处理之前需要将含硅晶片浸入HF酸中的问题。 本发明克服了多个CVD反应器中原位过程之间的表面钝化问题。

公开(公告)号：US06251751B1

公开(公告)日：2001-06-26

申请号：US09290778

申请日：1999-04-13

申请人： Jack Oon Chu ,  Khalid Ezzeldin Ismail ,  Kim Yang Lee ,  John Albrecht Ott

发明人： Jack Oon Chu ,  Khalid Ezzeldin Ismail ,  Kim Yang Lee ,  John Albrecht Ott

IPC分类号： H01L2176

CPC分类号： H01L21/76264 ,  H01L21/76281

摘要： A method for forming buried oxide regions below a single crystal semiconductor layer incorporating the steps of forming epitaxial layers having different rates of oxidation with the lower layer having a faster rate of oxidation and oxidizing the layers through an opening in a mask. A plurality of oxide isolated FET's may be formed. The invention reduces the problem of source/drain parasitic capacitance and short channel effects while isolating FET's and eliminating floating body effects of an FET by selectively oxidizing semiconductor layers.

摘要翻译： 一种用于在单晶半导体层下面形成掩埋氧化物区域的方法，其包括形成具有不同氧化速率的外延层的步骤，下层具有较快的氧化速率和通过掩模中的开口氧化该层。 可以形成多个氧化物隔离FET。 通过选择性地氧化半导体层，本发明减少了源极/漏极寄生电容和短沟道效应的问题，同时隔离FET并消除FET的浮体效应。

公开(公告)号：US07902012B2

公开(公告)日：2011-03-08

申请号：US12534562

申请日：2009-08-03

申请人： Qiqing Christine Ouyang ,  Jack Oon Chu

发明人： Qiqing Christine Ouyang ,  Jack Oon Chu

IPC分类号： H01L21/8234

CPC分类号： H01L21/823807 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/802 ,  Y10S438/933

摘要： A method for forming and the structure of a strained lateral channel of a field effect transistor, a field effect transistor and CMOS circuitry is described incorporating a drain, body and source region on a single crystal semiconductor substrate wherein a hetero-junction is formed between the source and body of the transistor, wherein the source region and channel are independently lattice strained with respect the body region. The invention reduces the problem of leakage current from the source region via the hetero junction and lattice strain while independently permitting lattice strain in the channel region for increased mobility via choice of the semiconductor materials and alloy composition.

摘要翻译： 描述了一种用于形成场效应晶体管，场效应晶体管和CMOS电路的应变横向沟道结构的方法，其在单晶半导体衬底上结合了漏极，主体和源极区域，其中在 晶体管的源极和主体，其中源极区域和沟道独立地相对于身体区域进行晶格应变。 本发明通过异质结和晶格应变来减少来自源极区的漏电流的问题，同时通过选择半导体材料和合金组成独立地允许沟道区域中的晶格应变以增加迁移率。

公开(公告)号：US07547930B2

公开(公告)日：2009-06-16

申请号：US12013230

申请日：2008-01-11

申请人： Jack Oon Chu

发明人： Jack Oon Chu

IPC分类号： H01L29/745

CPC分类号： H01L29/785 ,  H01L21/2807 ,  H01L21/28255 ,  H01L29/1029 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/41783 ,  H01L29/42384 ,  H01L29/42392 ,  H01L29/4908 ,  H01L29/4966 ,  H01L29/66628 ,  H01L29/66795 ,  H01L29/778 ,  H01L29/7787 ,  H01L29/7842 ,  H01L29/78642 ,  H01L29/78648 ,  H01L29/78684 ,  H01L29/78696

摘要： Structure and methods of fabrication are disclosed for an enhanced FET devices in which dopant impurities are prevented from diffusing through the gate insulator. The structure comprises a Si:C, or SiGe:C, layer which is sandwiched between the gate insulator and a layer which is doped with impurities in order to provide a preselected work function. It is further disclosed how this, and further improvements for FET devices, such as raised source/drain and multifaceted gate on insulator, MODFET on insulator are integrated with strained Si based layer on insulator technology.

摘要翻译： 公开了用于增强的FET器件的制造结构和方法，其中防止掺杂剂杂质通过栅极绝缘体扩散。 该结构包括夹在栅极绝缘体和掺杂杂质的层之间的Si：C或SiGe：C层，以提供预选的功函数。 还进一步公开了如何以及对FET器件的进一步改进，诸如凸起源极/漏极和绝缘体上的多面绝缘体，绝缘体上的MODFET与应变的基于Si的绝缘体上的技术集成。

公开(公告)号：US20090026495A1

公开(公告)日：2009-01-29

申请号：US12181489

申请日：2008-07-29

申请人： Jack Oon Chu ,  David R. DiMilia ,  Lijuan Huang

发明人： Jack Oon Chu ,  David R. DiMilia ,  Lijuan Huang

IPC分类号： H01L29/161

CPC分类号： H01L21/76256 ,  H01L21/2007

摘要： A method for forming strained Si or SiGe on relaxed SiGe on insulator (SGOI) or a SiGe on Si heterostructure is described incorporating growing epitaxial Si1-yGey layers on a semiconductor substrate, smoothing surfaces by Chemo-Mechanical Polishing, bonding two substrates together via thermal treatments and transferring the SiGe layer from one substrate to the other via highly selective etching using SiGe itself as the etch-stop. The transferred SiGe layer may have its upper surface smoothed by CMP for epitaxial deposition of relaxed Si1-yGey, and strained Si1-yGey depending upon composition, strained Si, strained SiC, strained Ge, strained GeC, and strained Si1-yGeyC or a heavily doped layer to make electrical contacts for the SiGe/Si heterojunction diodes.

摘要翻译： 描述了在半导体衬底上增长的外延Si1-yGey层，通过Chemo-Mechanical Polishing平滑表面，通过热粘合将两个衬底粘合在一起，在绝缘体上松弛的SiGe（SiO）或Si异质结构上的SiGe上形成应变Si或SiGe的方法 处理并通过使用SiGe本身作为蚀刻停止的高选择性蚀刻将SiGe层从一个衬底转移到另一衬底。 转移的SiGe层可以通过CMP平滑CMP，用于外延沉积弛豫Si1-yGey，并且应变Si1-yGey取决于组成，应变Si，应变SiC，应变Ge，应变GeC和应变Si1-yGeyC或重度 掺杂层以形成SiGe / Si异质结二极管的电接触。

公开(公告)号：US20080318374A1

公开(公告)日：2008-12-25

申请号：US12198857

申请日：2008-08-26

申请人： Jack Oon Chu ,  Bruce B. Doris ,  Meikei Ieong ,  Jing Wang

发明人： Jack Oon Chu ,  Bruce B. Doris ,  Meikei Ieong ,  Jing Wang

IPC分类号： H01L21/8238

CPC分类号： H01L29/7838 ,  H01L21/28017 ,  H01L29/105

摘要： MOSFET devices suitable for operation at gate lengths less than about 40 nm, and methods of their fabrication is being presented. The MOSFET devices include a ground plane formed of a monocrystalline Si based material. A Si based body layer is epitaxially disposed over the ground plane. The body layer is doped with impurities of opposite type than the ground plane. The gate has a metal with a mid-gap workfunction directly contacting a gate insulator layer. The gate is patterned to a length of less than about 40 nm, and possibly less than 20 nm. The source and the drain of the MOSFET are doped with the same type of dopant as the body layer. In CMOS embodiments of the invention the metal in the gate of the NMOS and the PMOS devices may be the same metal.

公开(公告)号：US07348629B2

公开(公告)日：2008-03-25

申请号：US11407473

申请日：2006-04-20

申请人： Jack Oon Chu ,  Bruce B. Doris ,  Meikei Ieong ,  Jing Wang

发明人： Jack Oon Chu ,  Bruce B. Doris ,  Meikei Ieong ,  Jing Wang

IPC分类号： H01L29/76

CPC分类号： H01L29/7838 ,  H01L21/28017 ,  H01L29/105

摘要： MOSFET devices suitable for operation at gate lengths less than about 40 nm, and methods of their fabrication is being presented. The MOSFET devices include a ground plane formed of a monocrystalline Si based material. A Si based body layer is epitaxially disposed over the ground plane. The body layer is doped with impurities of opposite type than the ground plane. The gate has a metal with a mid-gap workfunction directly contacting a gate insulator layer. The gate is patterned to a length of less than about 40 nm, and possibly less than 20 nm. The source and the drain of the MOSFET are doped with the same type of dopant as the body layer. In CMOS embodiments of the invention the metal in the gate of the NMOS and the PMOS devices may be the same metal.

摘要翻译： 适用于栅极长度小于约40nm的MOSFET器件及其制造方法。 MOSFET器件包括由单晶Si基材料形成的接地平面。 Si基体层外延地设置在接地平面上。 体层掺杂了与地平面相反的杂质。 栅极具有中间功能函数的金属，其直接接触栅极绝缘体层。 栅极被图案化成小于约40nm，并且可能小于20nm的长度。 MOSFET的源极和漏极掺杂有与体层相同类型的掺杂剂。 在本发明的CMOS实施例中，NMOS和PMOS器件的栅极中的金属可以是相同的金属。

公开(公告)号：US07084431B2

公开(公告)日：2006-08-01

申请号：US10832217

申请日：2004-04-26

申请人： Jack Oon Chu ,  Richard Hammond ,  Khalid EzzEldin Ismail ,  Steven John Koester ,  Patricia May Mooney ,  John A. Ott

发明人： Jack Oon Chu ,  Richard Hammond ,  Khalid EzzEldin Ismail ,  Steven John Koester ,  Patricia May Mooney ,  John A. Ott

IPC分类号： H01L27/15 ,  H01L29/06

CPC分类号： H01L29/7782 ,  H01L29/1025 ,  H01L29/1054

摘要： A layered structure for forming electronic devices thereon is provided. The layered structure includes an over-shoot layer, Si1−yGey, within a relaxed Si1−xGex layer, wherein y=X+Z and Z is in the range from 0.01 to 0.1 and X is from 0.35 to 0.5. The over-shoot layer has a thickness that is less than its critical thickness.

摘要翻译： 提供了用于在其上形成电子器件的分层结构。 层状结构包括在弛豫的Si 1-x Ge x x中的超射层，Si 1-y Y y Y y 其中y = X + Z，Z在0.01至0.1的范围内，X为0.35至0.5。 超拍层具有小于其临界厚度的厚度。