公开(公告)号：US5909131A

公开(公告)日：1999-06-01

申请号：US695823

申请日：1996-07-31

申请人： Lawrence A. Singer ,  Todd L. Brooks

发明人： Lawrence A. Singer ,  Todd L. Brooks

IPC分类号： G11C27/02

CPC分类号： G11C27/024

摘要： In a switched-capacitor input sampling structure, a resistor connected in series with the input structure, but after the output of the input switch limits the noise bandwidth of the input structure. The selected placement of the resistor does not appreciably limit the slewing or settling time of downstream circuit elements, resulting in a low noise bandwidth, high speed system.

摘要翻译： 在开关电容输入采样结构中，与输入结构串联的电阻器，但输入开关输出端限制输入结构的噪声带宽。 所选择的电阻放置不会明显限制下游电路元件的回转或稳定时间，导致低噪声带宽，高速系统。

公开(公告)号：US5847600A

公开(公告)日：1998-12-08

申请号：US638287

申请日：1996-04-26

申请人： Todd L. Brooks ,  Lawrence Singer

发明人： Todd L. Brooks ,  Lawrence Singer

IPC分类号： H03F3/00 ,  H03F3/45 ,  H03F3/72

CPC分类号： H03F3/4521 ,  H03F3/005 ,  H03F3/45188 ,  H03F3/45242 ,  H03F3/72 ,  H03F2203/45356 ,  H03F2203/45644 ,  H03F2203/45651 ,  H03F2203/45682

摘要： A two-stage switched-capacitor residue amplifier having novel circuitry in the first and second stages provides fast and accurate settling while configured with a large closed-loop gain, and also provides low power consumption while powered from a five volt supply. The invention is particularly well suited for use in a multi-stage, pipe-lined analog-to-digital converter (ADC) that converts multiple bits in the first pipeline stage. Complementary PMOS and NMOS differential pairs are used in the first and/or second stage to increase the current slew capability of the amplifier. Current mirror gain and/or positive feedback is used in the second stage to increase transonductance and bandwidth. Cascode transistors are used in the output of the first and/or second stages and active cascode gain enhancement is used in the first stage to increase dc gain and accuracy. The common mode level at the output of the second stage is controlled by injecting a pair of control currents (representative of the difference between a common-mode level actually at the output of the second stage and a desired common mode level) into a pair of mirror input nodes in the second stage. The common mode level of the first stage is controlled from a common node of a differential pair of the second stage. The two-stage amplifier of the invention provides a gain bandwidth product of 800 MHz, a closed-loop bandwidth of 50 MHz, a dc gain 90 dB, and a power consumption 80 mW.

摘要翻译： 在第一和第二阶段具有新颖电路的两级开关电容器残余放大器提供快速和准确的稳定，同时配置有大的闭环增益，并且在由五伏电源供电时也提供低功耗。 本发明特别适用于在第一流水线级中转换多个比特的多级管线模数转换器（ADC）。 互补PMOS和NMOS差分对用于第一和/或第二级以增加放大器的电流转换能力。 在第二阶段使用电流镜增益和/或正反馈来增加电导率和带宽。 串级晶体管用于第一级和/或第二级的输出，并且在第一级中使用有源共源共轭增益增强以增加直流增益和精度。 第二级输出端的共模电平通过将一对控制电流（代表第二级输出端的共模电平与期望的共模电平之间的差）代入一对 第二阶段的镜像输入节点。 第一级的共模级由第二级的差分对的公共节点控制。 本发明的两级放大器提供800MHz的增益带宽乘积，50MHz的闭环带宽，直流增益90dB，功耗80mW。

公开(公告)号：US5789981A

公开(公告)日：1998-08-04

申请号：US638195

申请日：1996-04-26

申请人： Lawrence Singer ,  Todd L. Brooks

发明人： Lawrence Singer ,  Todd L. Brooks

IPC分类号： H03F3/30 ,  H03F3/45

CPC分类号： H03F3/3001 ,  H03F2203/30096 ,  H03F2203/30129

摘要： A high-gain, low-power transconductance amplifier suitable for use in switched-capacitor circuits provides improved accuracy and high-speed operation. The transconductance amplifier includes an input circuit that receives an input voltage. A current mirror circuit is coupled to the input circuit. At least one active cascode circuit, coupled to the current mirror circuit, receives current from the current mirror circuit and provides an output current. The active cascode circuit provides gain enhancement to the transconductance amplifier by increasing the output impedance of the transconductance amplifier.

摘要翻译： 适用于开关电容电路的高增益，低功耗跨导放大器提供更高的精度和高速运行。 跨导放大器包括接收输入电压的输入电路。 电流镜电路耦合到输入电路。 耦合到电流镜电路的至少一个有源共源共栅电路从电流镜电路接收电流并提供输出电流。 有源共源共栅电路通过增加跨导放大器的输出阻抗来为跨导放大器提供增益增益。

公开(公告)号：US5359296A

公开(公告)日：1994-10-25

申请号：US119940

申请日：1993-09-10

申请人： Todd L. Brooks ,  Mathew A. Rybicki

发明人： Todd L. Brooks ,  Mathew A. Rybicki

IPC分类号： G05F3/26 ,  H03F3/343 ,  H03F3/345 ,  H03F3/16

CPC分类号： H03F3/345 ,  G05F3/26

摘要： A self-biased cascode current mirror includes a current mirror (60), and a cascode bias generator (50). The cascode bias generator (50) includes a resistor (51) to provide a bias voltage for the current mirror (60). The current mirror (60) includes cascode transistor (64) and two mirror transistors (62, 63). The bias voltage is approximately equal to a minimum saturation voltage of the cascode transistor (64) plus a gate-source voltage of the transistor (63) of the current mirror (60). The self-biased cascode current mirror (60) has a high output impedance and high voltage swing while providing low power consumption and requiring a small layout area.

摘要翻译： 自偏置共源共栅电流镜包括电流镜（60）和共源共栅偏压发生器（50）。 共射共栅偏压发生器（50）包括用于为电流镜（60）提供偏置电压的电阻（51）。 电流镜（60）包括共源共栅晶体管（64）和两个反射镜晶体管（62,63）。 偏置电压近似等于共源共栅晶体管（64）的最小饱和电压加上电流镜（60）的晶体管（63）的栅极 - 源极电压。 自偏置共源共栅电流镜（60）具有高输出阻抗和高电压摆幅，同时提供低功耗并且需要较小的布局面积。

公开(公告)号：US5283580A

公开(公告)日：1994-02-01

申请号：US951958

申请日：1992-09-28

申请人： Todd L. Brooks ,  Mathew A. Rybicki ,  H. Spence Jackson

发明人： Todd L. Brooks ,  Mathew A. Rybicki ,  H. Spence Jackson

IPC分类号： H03M1/68 ,  H03M1/74 ,  H03M1/76

CPC分类号： H03M1/682 ,  H03M1/747 ,  H03M1/765

摘要： A digital-to-analog converter (10) uses series-connected resistors (55-59) to implement conversion of most significant bits of a digital input signal to an equivalent analog output signal. Current sources (22-26) are used to implement conversion of least significant bits of the digital input signal to the analog output signal. After making a binary-to-thermometer code conversion of the least significant bits, first logic circuitry (70) provides control signals (SI) for controlling the switching of each of the current sources to either a first (42) or a second (44) node. After making a binary to `one of` code conversion of the most significant bits, second logic circuitry (86) provides control signals (SR) for respectively switching the first and second nodes to any two resistor nodes of the resistors. The resistors are connected between a reference voltage terminal and a third node where the analog output signal is developed.

摘要翻译： 数模转换器（10）使用串联电阻（55-59）来实现数字输入信号的最高有效位到等效模拟输出信号的转换。 电流源（22-26）用于实现数字输入信号的最低有效位到模拟输出信号的转换。 在对最低有效位进行二进制到温度计代码转换之后，第一逻辑电路（70）提供控制信号（SI），用于控制每个电流源到第一（42）或第二（44） ）节点。 在将二进制变成最高有效位的“代码转换”之后，第二逻辑电路（86）提供用于分别将第一和第二节点切换到电阻器的任何两个电阻器节点的控制信号（SR）。 电阻器连接在参考电压端子和显影模拟输出信号的第三节点之间。

公开(公告)号：US5187448A

公开(公告)日：1993-02-16

申请号：US829822

申请日：1992-02-03

申请人： Todd L. Brooks ,  Mathew A. Rybicki

发明人： Todd L. Brooks ,  Mathew A. Rybicki

IPC分类号： H03F1/22 ,  H03F3/45

CPC分类号： H03F3/45192 ,  H03F3/45183 ,  H03F3/4565 ,  H03F2203/30084 ,  H03F2203/30117 ,  H03F2203/45008 ,  H03F2203/45074 ,  H03F2203/45082 ,  H03F2203/45221 ,  H03F2203/45318 ,  H03F2203/45418 ,  H03F2203/45424 ,  H03F2203/45466 ,  H03F2203/45471 ,  H03F2203/45631 ,  H03F2203/45644

摘要： A differential amplifier (60,60') enhances common-mode stability by making two nodes (86,87) of a first stage low common-mode impedance nodes and thus shifting a common-mode dominant pole from the two nodes (86,87). The first stage includes an input portion (80,80') and a differential load (110,110'). The input portion (80,80') provides first and second currents respectively to the differential load (110,110') in response to a differential input voltage. The first and second currents have a differential component and a common-mode component. The differential load (110,110') converts the differential and common-mode components of the first and second currents into differential and common-mode voltages, respectively, and provides a high impedance to the differential component and a low impedance to the common-mode component.

公开(公告)号：US08482347B2

公开(公告)日：2013-07-09

申请号：US12930487

申请日：2011-01-07

申请人： Iuri Mehr ,  Sherif Galal ,  Todd L. Brooks

发明人： Iuri Mehr ,  Sherif Galal ,  Todd L. Brooks

IPC分类号： H03F1/14

CPC分类号： H03F3/187 ,  H03F1/305 ,  H03F3/72 ,  H03F2200/411 ,  H03F2203/7236

摘要： Disclosed is an amplifier designed to substantially reduce an ON/OFF transient. The amplifier comprises a drive block that includes a pre-driver and an output stage. The amplifier also comprises a bypass circuit that is coupled to an output of the pre-driver. The bypass circuit of the amplifier is selectively activated to reduce the ON/OFF transient. The bypass circuit may comprise an auxiliary output stage that can be coupled to provide selective activation. The amplifier may also be configured to provide multi-point offset compensation. Also disclosed is a related method. The amplifier and the related method may be incorporated into an audio amplifier used in a cellular telephone or other mobile audio device.

摘要翻译： 公开了一种设计用于大大减少ON / OFF瞬变的放大器。 该放大器包括一个包括一个预驱动器和一个输出级的驱动块。 放大器还包括耦合到预驱动器的输出的旁路电路。 选择性地激活放大器的旁路电路以减少ON / OFF瞬变。 旁路电路可以包括可以耦合以提供选择性激活的辅助输出级。 放大器还可以被配置为提供多点偏移补偿。 还公开了相关方法。 放大器和相关方法可以结合到用于蜂窝电话或其它移动音频设备的音频放大器中。

公开(公告)号：US08452428B2

公开(公告)日：2013-05-28

申请号：US12268305

申请日：2008-11-10

申请人： Hongwei Kong ,  Nelson Sollenberger ,  Todd L. Brooks ,  Yee Ling Cheung ,  Xicheng Jiang

发明人： Hongwei Kong ,  Nelson Sollenberger ,  Todd L. Brooks ,  Yee Ling Cheung ,  Xicheng Jiang

IPC分类号： G06F17/00 ,  G06F13/24 ,  G06F13/32 ,  G01R27/08 ,  H04M1/00

CPC分类号： G06F13/4072

摘要： Aspects of a method and system for detecting and identifying electronic accessories or peripherals utilizing a hardware audio CODEC are provided. In this regard, a hardware audio CODEC may be operable to compare one or more voltages on one or more biased pins of an accessory or peripheral port to one or more reference voltages and generate one or more digital representations of the one or more voltages on the biased one or more pins. An accessory or peripheral attached to the accessory or peripheral port may be identified based on the comparison and/or the generated one or more digital representations. The one or more bias voltages may be controlled based on a result of the comparison and/or the generated digital representations. The one or more bias voltages may be reduced after an attached accessory or peripheral has been identified.

摘要翻译： 提供了利用硬件音频CODEC来检测和识别电子附件或外围设备的方法和系统的方面。 在这方面，硬件音频编解码器可以用于将附件或外围端口的一个或多个偏置引脚上的一个或多个电压与一个或多个参考电压进行比较，并且生成一个或多个电压的一个或多个数字表示 偏置一个或多个引脚。 可以基于比较和/或所生成的一个或多个数字表示来识别附接到附件或外围端口的附件或外围设备。 可以基于比较的结果和/或所生成的数字表示来控制一个或多个偏置电压。 在附加附件或外围设备被识别之后，可以减小一个或多个偏置电压。

公开(公告)号：US07126377B2

公开(公告)日：2006-10-24

申请号：US11355174

申请日：2006-02-16

申请人： Todd L. Brooks ,  Anilkumar V. Tammineedi

发明人： Todd L. Brooks ,  Anilkumar V. Tammineedi

IPC分类号： H03K19/0175

CPC分类号： H03F1/3205 ,  H03F3/005 ,  H03F3/45475 ,  H03F3/505 ,  H03F2200/168 ,  H03F2200/331 ,  H03F2200/417 ,  H03F2200/453 ,  H03F2203/45101 ,  H03F2203/5031

摘要： A source-follower transistor based buffer provides high linearity. A replica transistor is used to generate a replica voltage substantially equal to the output voltage of the buffer. The replica voltage is level shifted by a level shift circuit and applied at the drain of the source-follower transistor to improve the linearity of the buffer. The buffer may be used in conjunction with a switched-capacitor sampling circuit. A damping circuit may be used to reduce charge glitches due to sampling. The damping circuit may be a low pass filter. The buffer may be used in an interface circuit that produces an output signal from an input signal and controls the level of the output signal.

公开(公告)号：US20120056672A1

公开(公告)日：2012-03-08

申请号：US12807403

申请日：2010-09-03

申请人： Sherif Galal ,  Alex Jianzhong Chen ,  Khaled Abdelfattah ,  Todd L. Brooks

发明人： Sherif Galal ,  Alex Jianzhong Chen ,  Khaled Abdelfattah ,  Todd L. Brooks

IPC分类号： H03F3/16

CPC分类号： H03F3/211 ,  H03F1/301 ,  H03F3/3022 ,  H03F2200/375 ,  H03F2200/453 ,  H03F2203/30015

摘要： Disclosed is a Class-AB/B amplifier comprising a first output stage including a first plurality of amplification devices and a second output stage including a second plurality of amplification devices. According to one embodiment, the first output stage operates when the Class-AB/B amplifier is in a quiescent state and the second output stage operates when the Class-AB/B amplifier is in an active state. The Class-AB/B amplifier also comprises a level shifting circuit that adjusts a control voltage of the second output stage, where the level shifting circuit is adapted to activate the second output stage when the Class-AB/B amplifier enters the active state. Embodiments of the Class-AB/B amplifier may include a level shifting circuit that implements either a fixed or signal-dependent level shift, and a quiescent control circuit that substantially eliminates any systematic offset arising from the active feedback circuit inside the replica bias circuit.