公开(公告)号：US20140039664A1

公开(公告)日：2014-02-06

申请号：US13564337

申请日：2012-08-01

申请人： THEODOROS E. ANEMIKOS ,  Jeanne P. Bickford ,  Douglas S. Dewey ,  Ernest A. Viau, JR.

发明人： THEODOROS E. ANEMIKOS ,  Jeanne P. Bickford ,  Douglas S. Dewey ,  Ernest A. Viau, JR.

IPC分类号： G06F19/00

CPC分类号： G01R31/2894 ,  G01R31/2855 ,  G01R31/2868 ,  G01R31/287 ,  G01R31/2879 ,  G01R31/31718 ,  G05B19/41875 ,  Y02P90/14 ,  Y02P90/265

摘要： Methods and systems optimize power usage in an integrated circuit design by sorting the integrated circuit devices after manufacture into relatively slow integrated circuit devices and relatively fast integrated circuit devices to classify the integrated circuit devices into different voltage bins. The methods and systems establish a bin-specific reliability testing processes for each of the voltage bins and test the integrated circuit devices using a tester. This allows the methods and systems to identify as defective ones of the integrated circuit devices that fail the bin-specific integrated circuit reliability testing processes of a corresponding voltage bin. The methods and systems remove the defective ones of the integrated circuit devices to allow only non-defective integrated circuit devices to remain and supply the non-defective integrated circuit devices to a customer.

摘要翻译： 方法和系统通过将制造后的集成电路器件分类为相对较慢的集成电路器件和相对较快的集成电路器件来将集成电路器件分类到不同的电压仓中来优化集成电路设计中的功率利用。 方法和系统为每个电压仓建立一个二进制特定的可靠性测试过程，并使用测试仪测试集成电路器件。 这允许方法和系统将不合格的集成电路设备中的缺陷识别为相应电压仓的专用集成电路可靠性测试过程。 所述方法和系统移除集成电路器件中的有缺陷的集成电路器件，以便只允许无故障的集成电路器件保持并向客户提供无缺陷的集成电路器件。

公开(公告)号：US08578314B1

公开(公告)日：2013-11-05

申请号：US13604814

申请日：2012-09-06

申请人： Jeanne P. Bickford ,  Gerald P. Pomichter, Jr. ,  Mark S. Styduhar ,  Bernhard J. Wunder

发明人： Jeanne P. Bickford ,  Gerald P. Pomichter, Jr. ,  Mark S. Styduhar ,  Bernhard J. Wunder

IPC分类号： G06F17/50

CPC分类号： G06F17/5072 ,  G06F2217/04

摘要： Systems and methods receive a design of a circuit layout. The circuit layout has some available spaces. Such systems and methods automatically insert capacitor arrays in the specified spaces. Each of the capacitor arrays has capacitor cells, and each of the capacitor cells has capacitor structures and a buried implant. The process of inserting the capacitor arrays comprises a process of forming the capacitor arrays to either: grow the capacitor arrays to the size of the specified spaces; grow the capacitor arrays to a specified capacitance value within the restriction of the length dimension or the width dimension of the specified spaces; or grow the capacitor arrays to a specified capacitance value, irrespective of dimensional length dimension or width dimension limitations (where the only limitations are the dimensions of the specified space).

摘要翻译： 系统和方法接收电路布局的设计。 电路布局有一些可用空间。 这些系统和方法会自动将电容器阵列插入指定的空间。 每个电容器阵列具有电容器单元，并且每个电容器单元具有电容器结构和埋入式植入物。 插入电容器阵列的过程包括形成电容器阵列的过程：将电容器阵列增长到指定空间的大小; 在指定空间的长度尺寸或宽度尺寸的限制内将电容器阵列增长到指定的电容值; 或将电容器阵列增长到指定的电容值，而不考虑尺寸长度尺寸或宽度尺寸限制（唯一限制是指定空间的尺寸）。

公开(公告)号：US08418090B2

公开(公告)日：2013-04-09

申请号：US13368413

申请日：2012-02-08

申请人： Jeanne P. Bickford ,  Jason D. Hibbeler ,  Juergen Koehl

发明人： Jeanne P. Bickford ,  Jason D. Hibbeler ,  Juergen Koehl

IPC分类号： G06F17/50

CPC分类号： G06F17/5081

摘要： A method of estimating integrated circuit yield comprises providing an integrated circuit layout and a set of systematic defects based on a manufacturing process. Next, the method represents a systematic defect by modifying structures in the integrated circuit layout to create modified structures. More specifically, for short-circuit-causing defects, the method pre-expands the structures when the structures comprise a higher systematic defect sensitivity level, and pre-shrinks the structures when the structures comprise a lower systematic defect sensitivity level. Following this, a critical area analysis is performed on the integrated circuit layout using the modified structures, wherein dot-throwing, geometric expansion, or Voronoi diagrams are used. The method then computes a fault density value, random defects and systematic defects are computed. The fault density value is subsequently compared to a predetermined value, wherein the predetermined value is determined using test structures and/or yield data from a target manufacturing process.

公开(公告)号：US08095907B2

公开(公告)日：2012-01-10

申请号：US11874950

申请日：2007-10-19

申请人： Jeanne P. Bickford ,  John R. Goss ,  Nazmul Habib ,  Robert McMahon

发明人： Jeanne P. Bickford ,  John R. Goss ,  Nazmul Habib ,  Robert McMahon

IPC分类号： G06F17/50

CPC分类号： G06F17/5045 ,  G01R31/2894

摘要： A method of reliability evaluation and system fail warning using on chip parametric monitors. The method includes determining impact of parametric variation on reliability by identifying key parametric questions to be answered by stress, identifying parametric macros for each parameter, and identifying layout sensitive areas of evaluation. The process can also include a set of parametric macros in one of a test site or a product to be stressed, testing the set of parametric macros prior to start of stress and at each stress read out, and setting life time parameter profile for technology.

摘要翻译： 使用片上参数监视器的可靠性评估和系统故障警告的方法。 该方法包括通过识别应力应答的关键参数问题来确定参数变化对可靠性的影响，识别每个参数的参数宏，以及识别布局敏感的评估区域。 该过程还可以包括一组测试点或要压力的产品中的参数宏，在开始应力之前和每次读出压力时测试一组参数宏，并设置技术的寿命参数轮廓。

公开(公告)号：US07960836B2

公开(公告)日：2011-06-14

申请号：US12045374

申请日：2008-03-10

申请人： Brent A. Anderson ,  Jeanne P. Bickford ,  Markus Buehler ,  Jason D. Hibbeler ,  Juergen Koehl ,  Edward J. Nowak

发明人： Brent A. Anderson ,  Jeanne P. Bickford ,  Markus Buehler ,  Jason D. Hibbeler ,  Juergen Koehl ,  Edward J. Nowak

IPC分类号： H01L23/52

CPC分类号： H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit including a first wire of a first level of wiring tracks, a second wire of a second level of wiring tracks, a third wire of a third level of wiring tracks, and a fourth wire located a first distance from the second wire in the second level of wiring tracks. A first via connects the first and second wires at a first location of the second wire. A second via connects the second and third wires at the first location, the second via is substantially axially aligned with the first via. A third via connecting the third and fourth wires at a second location of the fourth wire. A fourth via connecting the first and fourth wires at the second location, the fourth via is substantially axially aligned with the third via. The second, third, and fourth vias, and the third and Fourth wires form a path between the first and second wires redundant to the first via.

摘要翻译： 一种集成电路，包括第一级布线轨道的第一线，第二级布线轨道的第二线，第三级布线轨道的第三线和与第二线的第一距离的第四线 第二层线路。 第一通孔在第二导线的第一位置连接第一和第二导线。 第二通孔在第一位置处连接第二和第三导线，第二通孔基本上与第一通孔轴向对准。 第三通过在第四线的第二位置连接第三和第四导线。 第四通孔在第二位置处连接第一和第四导线，第四通孔基本上与第三通孔轴向对准。 第二，第三和第四通孔以及第三和第四导线形成第一和第二导线之间的路径，该路径对于第一通孔是冗余的。

公开(公告)号：US07656182B2

公开(公告)日：2010-02-02

申请号：US11689150

申请日：2007-03-21

申请人： Jeanne P. Bickford ,  John R. Goss ,  Nazmul Habib ,  Robert J. McMahon

发明人： Jeanne P. Bickford ,  John R. Goss ,  Nazmul Habib ,  Robert J. McMahon

IPC分类号： G01R31/26

CPC分类号： G01R31/2894 ,  G01R31/2831 ,  G01R31/30

摘要： Disclosed are testing method embodiments in which, during post-manufacture testing, parametric measurements are taken from on-chip parametric measurement elements and used to optimize manufacturing in-line parametric control learning and/or to optimize product screening processes. Specifically, these post-manufacture parametric measurements can be used to disposition chips without shipping out non-conforming products, without discarding conforming products, and without requiring high cost functional tests. They can also be used to identify yield sensitivities to parametric variations from design and to provide feedback for manufacturing line improvements based on the yield sensitivities. Additionally, a historical database regarding the key parameters that are monitored at both the fabrication and post-fabrication levels can be used to predict future yield and, thereby, to preemptively improve the manufacturing line and/or also to update supply chain forecasts.

摘要翻译： 公开了测试方法实施例，其中在后制造测试中，参数测量取自片上参数测量元件，并用于优化制造在线参数控制学习和/或优化产品筛选过程。 具体来说，这些后期制造参数测量可用于配置芯片，而不会丢弃不合格的产品，而不会丢弃符合要求的产品，并且不需要高成本的功能测试。 它们也可以用于识别来自设计的参数变化的产量敏感性，并且基于产量灵敏度为制造线改进提供反馈。 此外，关于在制造和制造后水平上监测的关键参数的历史数据库可用于预测未来产量，从而预先改进生产线和/或更新供应链预测。

公开(公告)号：US20090106712A1

公开(公告)日：2009-04-23

申请号：US11874950

申请日：2007-10-19

申请人： Jeanne P. Bickford ,  John R. Goss ,  Nazmul Habib ,  Robert McMahon

发明人： Jeanne P. Bickford ,  John R. Goss ,  Nazmul Habib ,  Robert McMahon

IPC分类号： G06F17/50

CPC分类号： G06F17/5045 ,  G01R31/2894

摘要： A method of reliability evaluation and system fail warning using on chip parametric monitors. The method includes determining impact of parametric variation on reliability by identifying key parametric questions to be answered by stress, identifying parametric macros for each parameter, and identifying layout sensitive areas of evaluation. The process can also include a set of parametric macros in one of a test site or a product to be stressed, testing the set of parametric macros prior to start of stress and at each stress read out, and setting life time parameter profile for technology.

摘要翻译： 使用片上参数监视器的可靠性评估和系统故障警告的方法。 该方法包括通过识别应力应答的关键参数问题来确定参数变化对可靠性的影响，识别每个参数的参数宏，以及识别布局敏感的评估区域。 该过程还可以包括一组测试点或要压力的产品中的参数宏，在开始应力之前和每次读出压力时测试一组参数宏，并设置技术的寿命参数轮廓。

公开(公告)号：US20090031274A1

公开(公告)日：2009-01-29

申请号：US12146921

申请日：2008-06-26

申请人： Andreas Arp ,  Jeanne P. Bickford ,  Markus Buehler ,  Juergen Koehl ,  Philipp Salz

发明人： Andreas Arp ,  Jeanne P. Bickford ,  Markus Buehler ,  Juergen Koehl ,  Philipp Salz

IPC分类号： G06F17/50

CPC分类号： G06F17/5077

摘要： A computer readable medium, system and associated method is provided for designing an integrated circuit with inserted loops. The method comprises the steps of inserting a loop with tagged wire segments and/or vias in a fully routed and DCR clean integrated circuit; performing a DRC; and fixing DRC violations by removing tagged wire segments and/or vias which contribute to a violation.

摘要翻译： 提供了一种用于设计具有插入环路的集成电路的计算机可读介质，系统和相关方法。 该方法包括以下步骤：将带有标记的线段和/或过孔的环路插入完全路由和DCR清洁集成电路中; 执行刚果民主共和国 并通过删除有助于违规的标记线段和/或过孔来修复DRC违规。

公开(公告)号：US07477961B2

公开(公告)日：2009-01-13

申请号：US11382963

申请日：2006-05-12

申请人： Thomas S. Barnett ,  Jeanne P. Bickford ,  William Y. Chang ,  Rashmi D. Chatty ,  Sebnem Jaji ,  Kerry A. Kravec ,  Wing L. Lai ,  Gie Lee ,  Brian M. Trapp ,  Alan J. Weger

发明人： Thomas S. Barnett ,  Jeanne P. Bickford ,  William Y. Chang ,  Rashmi D. Chatty ,  Sebnem Jaji ,  Kerry A. Kravec ,  Wing L. Lai ,  Gie Lee ,  Brian M. Trapp ,  Alan J. Weger

IPC分类号： G06F19/00

CPC分类号： G06F17/5081 ,  G06F2217/10

摘要： A method of modeling yield for semiconductor products includes determining expected faults for each of a plurality of library elements by running a critical area analysis on each of the library elements, and assessing, from the critical area analysis, an expected number of faults per unit area, and comparing the same to actual observed faults on previously manufactured semiconductor products. Thereafter, the expected number of faults for each library element is updated in response to observed yield. A database is established, which includes the die size and expected faults for each of the library elements. Integrated circuit product die size is estimated, and library elements to be used to create the integrated circuit die are selected. Fault and size data for each of the selected library elements are obtained, the adjusted estimated faults for each of the library elements are summed, and estimated yield is calculated.

摘要翻译： 一种用于半导体产品的产量建模的方法包括通过对每个库元件运行关键区域分析来确定多个库元件中的每一个元素的预期故障，以及从关键区域分析来估计每单位面积的预期故障数量 并将其与先前制造的半导体产品的实际观察到的故障进行比较。 此后，响应于观察到的产量，更新每个库元素的预期数量的故障。 建立了一个数据库，其中包括每个库元素的管芯大小和预期的故障。 集成电路产品芯片尺寸被估计，并且选择用于创建集成电路管芯的库元件。 获得每个所选库元素的故障和大小数据，对每个库元素的调整后的估计故障相加，并计算估计的收益率。

公开(公告)号：US20080150149A1

公开(公告)日：2008-06-26

申请号：US12045374

申请日：2008-03-10

申请人： Brent A. Anderson ,  Jeanne P. Bickford ,  Markus Buehler ,  Jason D. Hibbeler ,  Juergen Koehl ,  Edward J. Nowak

发明人： Brent A. Anderson ,  Jeanne P. Bickford ,  Markus Buehler ,  Jason D. Hibbeler ,  Juergen Koehl ,  Edward J. Nowak

IPC分类号： H01L23/52 ,  G06F17/50

CPC分类号： H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit including a first wire of a first level of wiring tracks, a second wire of a second level of wiring tracks, a third wire of a third level of wiring tracks, and a fourth wire located a first distance from the second wire in the second level of wiring tracks. A first via connects the first and second wires at a first location of the second wire. A second via connects the second and third wires at the first location, the second via is substantially axially aligned with the first via. A third via connecting the third and fourth wires at a second location of the fourth wire. A fourth via connecting the first and fourth wires at the second location, the fourth via is substantially axially aligned with the third via. The second, third, and fourth vias, and the third and Fourth wires form a path between the first and second wires redundant to the first via.

摘要翻译： 一种集成电路，包括第一级布线轨道的第一线，第二级布线轨道的第二线，第三级布线轨道的第三线和与第二线的第一距离的第四线 第二层线路。 第一通孔在第二导线的第一位置连接第一和第二导线。 第二通孔在第一位置处连接第二和第三导线，第二通孔基本上与第一通孔轴向对准。 第三通过在第四线的第二位置连接第三和第四导线。 第四通孔在第二位置处连接第一和第四导线，第四通孔基本上与第三通孔轴向对准。 第二，第三和第四通孔以及第三和第四导线形成第一和第二导线之间的路径，该路径对于第一通孔是冗余的。