公开(公告)号：US07276392B2

公开(公告)日：2007-10-02

申请号：US11261191

申请日：2005-10-28

申请人： Sheng Teng Hsu ,  Jong-Jan Lee ,  Jer-Shen Maa ,  Douglas J. Tweet

发明人： Sheng Teng Hsu ,  Jong-Jan Lee ,  Jer-Shen Maa ,  Douglas J. Tweet

IPC分类号： H01L21/00 ,  H01L21/84 ,  H01L21/20 ,  H01L21/36

CPC分类号： H01L31/1136

摘要： A floating body germanium (Ge) phototransistor with a photo absorption threshold bias region, and an associated fabrication process are presented. The method includes: providing a p-doped Silicon (Si) substrate; selectively forming an insulator layer overlying a first surface of the Si substrate; forming an epitaxial Ge layer overlying the insulator layer; forming a channel region in the Ge layer; forming a gate dielectric, gate electrode, and gate spacers; forming source/drain (S/D) regions in the Ge layer; and, forming a photo absorption threshold bias region in the Ge layer, adjacent the channel region. In one aspect, the second S/D region has a length, longer than the first S/D length. The photo absorption threshold bias region underlies the second S/D region. Alternately, the second S/D region is separated from the channel by an offset, and the photo absorption threshold bias region is the offset in the Ge layer, after a light p-doping.

公开(公告)号：US07271023B2

公开(公告)日：2007-09-18

申请号：US11174035

申请日：2005-07-01

申请人： Jong-Jan Lee ,  Sheng Teng Hsu ,  Jer-Shen Maa ,  Douglas J. Tweet

发明人： Jong-Jan Lee ,  Sheng Teng Hsu ,  Jer-Shen Maa ,  Douglas J. Tweet

IPC分类号： H01L21/00 ,  H01L21/84 ,  H01L21/331 ,  H01L21/76 ,  H01L21/20 ,  H01L21/36

CPC分类号： H01L31/1136 ,  H01L31/028 ,  H01L31/1808 ,  Y02E10/547

摘要： A floating body germanium (Ge) phototransistor and associated fabrication process are presented. The method includes: providing a silicon (Si) substrate; selectively forming an insulator layer overlying the Si substrate; forming an epitaxial Ge layer overlying the insulator layer using a liquid phase epitaxy (LPE) process; forming a channel region in the Ge layer; forming a gate dielectric, gate electrode, and gate spacers overlying the channel region; and, forming source/drain regions in the Ge layer. The LPE process involves encapsulating the Ge with materials having a melting temperature greater than a first temperature, and melting the Ge using a temperature lower than the first temperature. The LPE process includes: forming a dielectric layer overlying deposited Ge; melting the Ge; and, in response to cooling the Ge, laterally propagating an epitaxial growth front into the Ge from an underlying Si substrate surface.

公开(公告)号：US07265030B2

公开(公告)日：2007-09-04

申请号：US10894685

申请日：2004-07-20

申请人： Jer-Shen Maa ,  Jong-Jan Lee ,  Douglas J. Tweet ,  Sheng Teng Hsu

发明人： Jer-Shen Maa ,  Jong-Jan Lee ,  Douglas J. Tweet ,  Sheng Teng Hsu

IPC分类号： H01L21/46

CPC分类号： H01L21/76254 ,  Y10S438/977

摘要： A method of fabricating a silicon-on-glass layer via layer transfer includes depositing a layer of SiGe on a silicon substrate; relaxing the SiGe layer; depositing a layer of silicon on the relaxed SiGe layer; implanting hydrogen ions in a second hydrogen implantation step to facilitate splitting of the wafer; bonding a glass substrate to the strained silicon layer to form a composite wafer; splitting the composite wafer to provide a split wafer; and processing the split wafer to prepare it for subsequent device fabrication.

摘要翻译： 通过层转移制造硅 - 玻璃层的方法包括在硅衬底上沉积SiGe层; 放松SiGe层; 在松弛的SiGe层上沉积一层硅; 在第二氢注入步骤中注入氢离子以促进晶片的分裂; 将玻璃基板粘合到应变硅层以形成复合晶片; 分离复合晶片以提供分离晶片; 并处理分离晶片以准备其用于随后的器件制造。

公开(公告)号：US07186611B2

公开(公告)日：2007-03-06

申请号：US11240969

申请日：2005-09-30

申请人： Sheng Teng Hsu ,  Jong-Jan Lee ,  Jer-Shen Maa ,  Douglas J. Tweet

发明人： Sheng Teng Hsu ,  Jong-Jan Lee ,  Jer-Shen Maa ,  Douglas J. Tweet

IPC分类号： H01L21/329

CPC分类号： H01L31/1126 ,  C30B19/00 ,  C30B29/08 ,  H01L21/02381 ,  H01L21/02488 ,  H01L21/02532 ,  H01L21/02623 ,  H01L21/02639 ,  H01L21/30625 ,  H01L21/7624 ,  H01L27/14683 ,  H01L27/14689 ,  H01L29/16 ,  H01L29/78 ,  H01L31/105 ,  H01L31/1804 ,  H01L31/1808 ,  Y02E10/547

摘要： A high-density Germanium (Ge)-on-Insulator (GOI) photodiode array and corresponding fabrication method are provided. The method includes: forming an array of pixel driver nMOST devices, each device having a gate connected to a row line in a first orientation, a first source/drain (S/D) region, and a second S/D region connected to Vdd; forming a P-I-N Ge diode for each pixel as follows: forming a n+ region; forming an intrinsic Ge region overlying the n+ region; forming a p+ junction in the intrinsic Ge; and, isolating the P-I-N Ge diodes; and, forming an Indium Tin oxide (ITO) column in a second orientation, about orthogonal to the first orientation, overlying the P-I-N Ge diodes.

摘要翻译： 提供了高密度锗（Ge）绝缘体（GOI）光电二极管阵列和相应的制造方法。 该方法包括：形成像素驱动器nMOST器件的阵列，每个器件具有以第一取向连接到行线的栅极，第一源极/漏极（S / D）区域和连接到Vdd的第二S / D区域 ; 如下形成每个像素的P-I-N Ge二极管：形成n +区; 形成覆盖n +区域的本征Ge区域; 在本征Ge中形成p +结; 并隔离P-I-N Ge二极管; 并且以与第一取向正交的第二取向形成铟锡氧化物（ITO）柱，覆盖P-I-N Ge二极管。

公开(公告)号：US07008813B1

公开(公告)日：2006-03-07

申请号：US11069424

申请日：2005-02-28

申请人： Jong-Jan Lee ,  Jer-Shen Maa ,  Douglas J. Tweet ,  Sheng Teng Hsu

发明人： Jong-Jan Lee ,  Jer-Shen Maa ,  Douglas J. Tweet ,  Sheng Teng Hsu

IPC分类号： H01L21/00

CPC分类号： H01L27/14689 ,  H01L31/105 ,  H01L31/1804 ,  Y02E10/547 ,  Y02P70/521 ,  Y10S148/101

摘要： A method of fabricating a germanium photodetector includes preparing a silicon wafer as a silicon substrate; depositing a layer of silicon nitride on the silicon substrate; patterning and etching the silicon nitride layer; depositing a first germanium layer on the silicon nitride layer; patterning and etching the germanium layer wherein a portion of the germanium layer is in direct physical contact with the silicon substrate; depositing a layer of silicon oxide on the germanium layer wherein the germanium layer is encapsulated by the silicon oxide layer; annealing the structure at a temperature wherein the germanium melts and the other layers remain solid; growing a second, single-crystal layer of germanium on the structure by liquid phase epitaxy; selectively removing the silicon oxide layer; and completing the germanium photodetector.

摘要翻译： 制造锗光电检测器的方法包括制备硅晶片作为硅衬底; 在硅衬底上沉积氮化硅层; 图案化和蚀刻氮化硅层; 在所述氮化硅层上沉积第一锗层; 图案化和蚀刻锗层，其中锗层的一部分与硅衬底直接物理接触; 在锗层上沉积氧化硅层，其中锗层被氧化硅层包封; 在锗熔融并且其它层保持固体的温度下退火该结构; 通过液相外延在结构上生长第二个锗单晶层; 选择性地除去氧化硅层; 并完成锗光电探测器。

公开(公告)号：US06967112B2

公开(公告)日：2005-11-22

申请号：US10794158

申请日：2004-03-03

申请人： Jer-Shen Maa ,  Jong-Jan Lee ,  Douglas J. Tweet ,  Sheng Teng Hsu

发明人： Jer-Shen Maa ,  Jong-Jan Lee ,  Douglas J. Tweet ,  Sheng Teng Hsu

IPC分类号： H01L21/00 ,  H01L21/66 ,  H01L31/0352 ,  H01L31/26

CPC分类号： H01L31/035236 ,  B82Y10/00 ,  B82Y20/00

摘要： A 3D quantum dot optical path structure is provided, along with a method for selectively forming a 3D quantum dot optical path. The method comprises: forming a single crystal Si substrate with a surface; forming a Si feature in the substrate, such as a via, trench, or pillar; forming dots from a Ge or SiGe material overlying the Si feature; and, forming an optical path that includes the dots. In some aspects of the method, the Si feature has defect sites. For example, the Si feature may be formed with a miscut angle. As a result of the miscut angle, steps are formed in the Si feature plane. Then, the dots are formed in the Si feature steps. The miscut angle is in the range between 0.1 and 5 degrees, and the spacing between steps is in the range between 1 and 250 nanometers (nm).

摘要翻译： 提供了3D量子点光路结构以及用于选择性地形成3D量子点光路的方法。 该方法包括：用表面形成单晶Si衬底; 在衬底中形成Si特征，例如通孔，沟槽或柱; 从覆盖Si特征的Ge或SiGe材料形成点; 并且形成包括点的光路。 在该方法的某些方面，Si特征具有缺陷位点。 例如，Si特征可以形成为错误角度。 作为误差角的结果，在Si特征平面中形成台阶。 然后，在Si特征步骤中形成点。 误差角在0.1和5度之间的范围内，并且步骤之间的间隔在1和250纳米（nm）之间的范围内。

公开(公告)号：US06903384B2

公开(公告)日：2005-06-07

申请号：US10345551

申请日：2003-01-15

申请人： Sheng Teng Hsu ,  Jong-Jan Lee ,  Douglas J. Tweet ,  Jer-shen Maa

发明人： Sheng Teng Hsu ,  Jong-Jan Lee ,  Douglas J. Tweet ,  Jer-shen Maa

IPC分类号： H01L21/322 ,  H01L21/762 ,  H01L21/8238 ,  H01L27/092 ,  H01L27/12 ,  H01L29/10 ,  H01L29/78 ,  H01L29/786 ,  H01L31/0312

CPC分类号： H01L29/1054 ,  H01L21/76224 ,  H01L21/823807 ,  H01L21/823842 ,  H01L21/823878 ,  H01L27/1203 ,  H01L29/78645

摘要： A dual gate strained-Si MOSFET with thin SiGe dislocation regions and a method for fabricating the same are provided. The method comprises: forming a first layer of relaxed SiGe overlying a substrate, having a thickness of less than 5000 Å; forming a second layer of relaxed SiGe overlying the substrate and adjacent to the first layer of SiGe, having a thickness of less than 5000 Å; forming a layer of strained-Si overlying the first and second SiGe layers; forming a shallow trench isolation region interposed between the first SiGe layer and the second SiGe layer; forming an n-well in the substrate and the overlying first layer of SiGe; forming a p-well in the substrate and the overlying second layer of SiGe; forming channel regions, in the strained-Si, and forming PMOS and NMOS transistor source and drain regions.

摘要翻译： 提供具有薄SiGe位错区域的双栅应变Si MOSFET及其制造方法。 该方法包括：形成覆盖衬底的第一层松弛SiGe，厚度小于5000; 形成第二层弛豫的SiGe，覆盖衬底并与第一层SiGe相邻，厚度小于5000; 形成层叠在第一和第二SiGe层上的应变层; 形成介于所述第一SiGe层和所述第二SiGe层之间的浅沟槽隔离区域; 在衬底和上覆的第一层SiGe中形成n阱; 在衬底和SiGe的上覆第二层中形成p阱; 在应变Si中形成沟道区，并形成PMOS和NMOS晶体管的源极和漏极区。

公开(公告)号：US06767802B1

公开(公告)日：2004-07-27

申请号：US10665944

申请日：2003-09-19

申请人： Jer-Shen Maa ,  Jong-Jan Lee ,  Douglas J. Tweet ,  Sheng Teng Hsu

发明人： Jer-Shen Maa ,  Jong-Jan Lee ,  Douglas J. Tweet ,  Sheng Teng Hsu

IPC分类号： H01L2176

CPC分类号： H01L21/76254

摘要： Methods of forming a SiGe layer overlying an insulator are provided. A layer of SiGe is deposited on a substrate and implanted with ion to form a defect region within the SiGe material below its surface. The SiGe layer is then patterned and transferred by contact bonding to an insulator on a second substrate. After contact bonding the structure is annealed to split the SiGe layer along the defect region. The splitting anneal will relax the SiGe layer. Additional annealing at higher temperatures may be used to further relax the SiGe layer. A layer of strained silicon may then be epitaxial deposited on the resulting structure of relaxed SiGe on insulator. Another method provides for epitaxially depositing a layer of silicon over the SiGe layer prior to patterning. The silicon layer would then be bonded to the insulator on the second substrate. The splitting anneal and additional anneals, if any, should then induce strain into the silicon layer. The silicon layer would then remain over the insulator after the SiGe layer is removed.

摘要翻译： 提供了形成覆盖在绝缘体上的SiGe层的方法。 将一层SiGe沉积在衬底上并注入离子以在其表面下方的SiGe材料内形成缺陷区。 然后，通过接触粘合将SiGe层图案化并转移到第二基板上的绝缘体。 在接合之后，将结构退火以沿着缺陷区域分离SiGe层。 分裂退火将使SiGe层松弛。 可以在较高温度下进行额外退火以进一步松弛SiGe层。 然后可以将绝缘体上的松散SiGe结构外延沉积一层应变硅。 另一种方法提供在图案化之前在SiGe层上外延沉积硅层。 然后将硅层与第二基板上的绝缘体接合。 分裂退火和额外的退火（如果有的话）应该在硅层中诱导应变。 在除去SiGe层之后，硅层将保留在绝缘体上。

公开(公告)号：US07906825B2

公开(公告)日：2011-03-15

申请号：US12630893

申请日：2009-12-04

申请人： Douglas J. Tweet ,  Jer-Shen Maa ,  Jong-Jan Lee ,  Sheng Teng Hsu

发明人： Douglas J. Tweet ,  Jer-Shen Maa ,  Jong-Jan Lee ,  Sheng Teng Hsu

IPC分类号： H01L27/14

CPC分类号： H01L31/1055 ,  H01L27/14643 ,  H01L27/14689

摘要： A germanium (Ge) short wavelength infrared (SWIR) imager and associated fabrication process are provided. The imager comprises a silicon (Si) substrate with doped wells. An array of pin diodes is formed in a relaxed Ge-containing film overlying the Si substrate, each pin diode having a flip-chip interface. There is a Ge/Si interface, and a doped Ge-containing buffer interposed between the Ge-containing film and the Ge/Si interface. An array of Si CMOS readout circuits is bonded to the flip-chip interfaces. Each readout circuit has a zero volt diode bias interface.

摘要翻译： 提供锗（Ge）短波长红外（SWIR）成像器和相关制造工艺。 该成像器包括具有掺杂阱的硅（Si）衬底。 在位于Si衬底上的松弛的含Ge膜中形成一个pin二极管阵列，每个pin二极管具有倒装芯片接口。 存在Ge / Si界面和插入含Ge膜和Ge / Si界面之间的含掺杂Ge的缓冲层。 Si CMOS读出电路阵列结合到倒装芯片接口。 每个读出电路都具有零伏二极管偏置接口。

公开(公告)号：US07786469B2

公开(公告)日：2010-08-31

申请号：US12236480

申请日：2008-09-23

申请人： Jer-Shen Maa ,  Jinke Tang ,  Jong-Jan Lee ,  Douglas J. Tweet ,  Sheng Teng Hsu

发明人： Jer-Shen Maa ,  Jinke Tang ,  Jong-Jan Lee ,  Douglas J. Tweet ,  Sheng Teng Hsu

IPC分类号： H01L31/00

CPC分类号： H01L31/035254 ,  B82Y20/00 ,  H01L27/14649 ,  H01L31/028 ,  H01L31/101 ,  H01L31/1804 ,  Y02P70/521

摘要： A silicon/germanium (SiGe) superlattice thermal sensor is provided with a corresponding fabrication method. The method forms an active CMOS device in a first Si substrate, and a SiGe superlattice structure on a second Si-on-insulator (SOI) substrate. The first substrate is bonded to the second substrate, forming a bonded substrate. An electrical connection is formed between the SiGe superlattice structure and the CMOS device, and a cavity is formed between the SiGe superlattice structure and the bonded substrate.

摘要翻译： 硅/锗（SiGe）超晶格热传感器具有相应的制造方法。 该方法在第一Si衬底中形成有源CMOS器件，并在第二绝缘体上（SOI）衬底上形成SiGe超晶格结构。 第一基板与第二基板接合，形成接合基板。 在SiGe超晶格结构和CMOS器件之间形成电连接，并且在SiGe超晶格结构和键合衬底之间形成空穴。