Abstract:
A liquid crystal display screen includes an upper board, a lower board opposite to the upper board, and a liquid crystal layer located between the upper board and the lower board. The upper board includes a touch panel. The touch panel includes a plurality of transparent electrodes. At least one of the transparent electrodes includes a carbon nanotube structure.
Abstract:
A display device includes a circuit board connecting structure. The circuit board connecting structure includes a first circuit board, a soldering layer, and a second circuit board. The first circuit board includes a baseboard and a plurality of parallel elongate first electrodes defined at a predetermined area. The second circuit board includes a plurality of parallel elongate second electrodes positioned at the predetermined area. The second electrodes are electrically connected to the corresponding first electrodes via the soldering layer. A space defined by the projection of the second electrodes to the baseboard of the first circuit board is filled in by the soldering layer.
Abstract:
A method for making a liquid crystal display screen is provided. A touch panel including at least one carbon nanotube structure layer is prepared. A first polarizer is applied on a surface of the touch panel. A thin film transistor panel including a number of thin film transistors is prepared. A liquid crystal layer is placed between the first polarizer and the thin film transistors.
Abstract:
An exemplary electro-wetting display (EWD) device includes an upper substrate, a lower substrate opposite to the upper substrate, a plurality of side walls interposed between the upper and lower substrates and cooperating with the upper and lower substrates to form a plurality of pixel units, a first polar liquid disposed in the pixel units, a second, colored, non-polar liquid disposed in the pixel units and being immiscible with the first liquid, and a plurality of scanning lines disposed on the lower substrate and parallel to and spaced apart from each other for providing scanning signals to the pixel units. Each of the pixel units corresponds to at least part of a corresponding previous scanning line.
Abstract:
A process for forming an in-plane switching mode liquid crystal display (IPS-LCD), which defines pixel portions of the common and data electrodes by the same photo-masking and lithography procedure, is disclosed. Accordingly, the misalignment can be avoid. An in-plane switching mode liquid crystal display (IPS-LCD) is also disclosed. The IPS-LCD includes a storage capacitor consisting of storage-capacitor portions of the common and data electrode structures, which is disposed outside the pixel region so as to enhance the aperture ratio of the pixel region.
Abstract:
A repair structure for repairing data lines and scan lines comprised in a thin film transistor-liquid crystal display (TFT-LCD) is provided. The repair structure includes a first conducting repair structure formed simultaneously with a gate conducting structure of the thin film transistor-liquid crystal display, an insulating layer formed on the first conducting repair structure, and a second conducting repair structure formed on the insulating layer simultaneously with a data conducting structure of the thin film transistor-liquid crystal display and connected with the data conducting structure, wherein a plurality of overlap regions having the insulating layer between the fist conducting repair structure and the second conducting repair structure are formed, wherein when the data conducting structure positioned in the overlap regions is broken, the insulating layer in the overlap regions is destroyed to make electric connection between the first conducting repair structure and the second conducting repair structure.
Abstract:
A method of fabricating cup shape cylindrical capacitor of high density Dynamic Random Access Memory (DRAM) cells is disclosed. The cup shape capacitor shape is achieved by first depositing a first polysilicon layer on a silicon substrate; a third dielectric layer is then formed overlaying the first polysilicon layer, and defined third dielectric crowns by the conventional lithography and etching techniques; a second polysilicon layer is deposited overlaying the third dielectric crowns and first polysilicon layer; the first polysilicon and second polysilicon layers are then vertically anisotropically etchback to define storage nodes of the cylindrical capacitors; the third dielectric crowns are removed; finally, the capacitor dielectric layer and the polysilicon top plate of the capacitor are formed to complete the cup shape cylindrical capacitor formation for high density DRAM applications.
Abstract:
A simplified tri-layer process for forming a thin film transistor matrix for a liquid crystal display is disclosed. By using a backside exposure technique, the masking step for patterning an etch stopper layer can be omitted. After forming an active region including a gate electrode and a scan line on the front side of a substrate, and sequentially applying an etch stopper layer and a photoresist layer over the resulting structure, the backside exposure is performed by exposing from the back side of the substrate. A portion of photoresist is shielded by the active region from exposure so that an etch stopper structure having a shape similar to the shape of the active region is formed without any photo-masking and lithographic procedure. Therefore, the above self-aligned effect allows one masking step to be reduced so as to simplify the process.
Abstract:
A method for fabricating a capacitor electrode on a semiconductor substrate includes the steps of: forming a conducting layer over the semiconductor substrate; forming a photoresist layer over the conducting layer; pattering the photoresist layer through an interfering exposure step; and pattering the conducting layer using the patterned photoresist layer as a mask, thereby forming a capacitor electrode.
Abstract:
A method of fabricating a rugged capacitor structure of high density Dynamic Random Access Memory (DRAM) cells is disclosed. First, MOSFETs, wordlines and bitlines are formed on a semiconductor silicon substrate. Next, a dielectric layer and a doped polysilicon layer are sequentially deposited over the entire silicon substrate. The dielectric layer and doped polysilicon layer are then partially etched to open source contact windows. Then, a polysilicon layer is deposited overlaying the doped polysilicon layer and filling into the source contact windows. Next, the polysilicon layer and doped polysilicon layers are partially etched to define bottom electrodes of the capacitors. Next, tilt angle implantation is performed to implant impurities into top surface and four sidewalls of the polysilicon layer and doped polysilicon layer. Next, a rugged polysilicon layer is deposited overlaying the polysilicon, doped polysilicon and third dielectric layers. Next, the polysilicon layer is anisotropically etched by using the rugged polysilicon layer as an etching mask to transfer rugged surface profile from the rugged polysilicon layer to the polysilicon layer. Finally, an interelectrode dielectric layer and a third polysilicon layer as top electrodes of the capacitors are sequentially formed to complete the rugged capacitor for high density DRAM applications.