公开(公告)号：US20060014359A1

公开(公告)日：2006-01-19

申请号：US10891540

申请日：2004-07-15

申请人： Jiang Yan ,  Danny Shum

发明人： Jiang Yan ,  Danny Shum

IPC分类号： H01L21/76

CPC分类号： H01L21/02381 ,  H01L21/02532 ,  H01L21/02639

摘要： A semiconductor device can be formed without use of an STI process. An insulating layer is formed over a semiconductor body. Portions of the insulating layer are removed to expose the semiconductor body, e.g., to expose bare silicon. A semiconductor material, e.g., silicon, is grown over the exposed semiconductor body. A device, such as a transistor, can then be formed in the grown semiconductor material.

摘要翻译： 可以不使用STI工艺来形成半导体器件。 在半导体本体上形成绝缘层。 绝缘层的一部分被去除以暴露半导体本体，例如露出裸硅。 半导体材料，例如硅，生长在暴露的半导体本体上。 然后可以在生长的半导体材料中形成诸如晶体管的器件。

公开(公告)号：US09419095B2

公开(公告)日：2016-08-16

申请号：US14119864

申请日：2012-12-12

申请人： Chunlong Li ,  Junfeng Li ,  Jiang Yan ,  Chao Zhao

发明人： Chunlong Li ,  Junfeng Li ,  Jiang Yan ,  Chao Zhao

IPC分类号： H01L21/338 ,  H01L29/66 ,  H01L29/423 ,  H01L29/51 ,  H01L21/28

CPC分类号： H01L29/66545 ,  H01L21/28123 ,  H01L29/42364 ,  H01L29/513 ,  H01L29/518

摘要： A method for manufacturing a dummy gate in a gate-last process and a dummy gate in a gate-last process are provided. The method includes: providing a semiconductor substrate; growing a gate oxide layer on the semiconductor substrate; depositing bottom-layer amorphous silicon on the gate oxide layer; depositing an ONO structured hard mask on the bottom-layer amorphous silicon; depositing top-layer amorphous silicon on the ONO structured hard mask; depositing a hard mask layer on the top-layer amorphous silicon; forming photoresist lines on the hard mask layer, and trimming the formed photoresist lines so that the trimmed photoresist lines a width less than or equal to 22 nm; and etching the hard mask layer, the top-layer amorphous silicon, the ONO structured hard mask and the bottom-layer amorphous silicon in accordance with the trimmed photoresist lines, and removing the photoresist lines, the hard mask layer and the top-layer amorphous silicon.

摘要翻译： 提供了一种在门最后处理中制造伪栅极的方法和在栅极最后工艺中的伪栅极。 该方法包括：提供半导体衬底; 在半导体衬底上生长栅极氧化层; 在栅极氧化物层上沉积底层非晶硅; 在底层非晶硅上沉积ONO结构的硬掩模; 在ONO结构化的硬掩模上沉积顶层非晶硅; 在顶层非晶硅上沉积硬掩模层; 在硬掩模层上形成光致抗蚀剂线，并修整所形成的光致抗蚀剂线，使得修整的光致抗蚀剂线的宽度小于或等于22nm; 并根据修整的光致抗蚀剂线蚀刻硬掩模层，顶层非晶硅，ONO结构的硬掩模和底层非晶硅，并除去光致抗蚀剂线，硬掩模层和顶层无定形 硅。

公开(公告)号：US09070744B2

公开(公告)日：2015-06-30

申请号：US13519573

申请日：2011-08-03

申请人： Jiang Yan

发明人： Jiang Yan

IPC分类号： H01L21/76 ,  H01L21/762

CPC分类号： H01L21/76232

摘要： The present invention relates to a shallow trench isolation structure, manufacturing method thereof and a device based on the structure. The present invention provides a method for manufacturing a shallow trench isolation (STI) structure, characterized in comprising the following steps: providing a semiconductor substrate; forming an insulating medium on said semiconductor substrate; etching a part of the insulating medium by using a mask to expose the semiconductor substrate thereunder, the unetched insulating medium forming STI regions; and epitaxially growing a semiconductor layer on said semiconductor substrate between said STI regions as an active region. With the method provided by the present invention, the problem of filling a small-size trench is solved and the problem of STI step height is overcome.

摘要翻译： 本发明涉及一种浅沟槽隔离结构，其制造方法和基于该结构的器件。 本发明提供一种制造浅沟槽隔离（STI）结构的方法，其特征在于包括以下步骤：提供半导体衬底; 在所述半导体衬底上形成绝缘介质; 通过使用掩模蚀刻绝缘介质的一部分以暴露其下的半导体衬底，形成STI区的未蚀刻绝缘介质; 并且在所述STI区域之间的所述半导体衬底上外延生长半导体层作为有源区。 利用本发明提供的方法，解决了填充小尺寸沟槽的问题，克服了STI步长的问题。

公开(公告)号：US08802578B2

公开(公告)日：2014-08-12

申请号：US13695191

申请日：2012-07-26

申请人： Zuozhen Fu ,  Huaxiang Yin ,  Jiang Yan

发明人： Zuozhen Fu ,  Huaxiang Yin ,  Jiang Yan

IPC分类号： H01L21/203 ,  H01L21/02 ,  C23C14/34 ,  C23C14/54 ,  C23C14/06 ,  C23C14/18

CPC分类号： H01L21/02186 ,  C23C14/0641 ,  C23C14/18 ,  C23C14/34 ,  C23C14/54 ,  H01L21/2855

摘要： A method for forming titanium nitride by PVD is disclosed, comprising: generating ions of a noble gas by glow discharge under a vacuum condition that a nitrogen gas and the noble gas are supplied; nitriding a surface of a wafer and a surface of a titanium target with the nitrogen gas; bombarding the surface of the titanium target with the ions of the noble gas after they are accelerated in an electric field so that titanium ions and titanium nitride are sputtered; and forming a titanium nitride layer by depositing titanium nitride on the surface of the wafer in a magnetic field, while titanium ions are injected into the surface of the wafer so that stress is introduced into the titanium nitride layer, wherein non-crystallization fraction of the titanium nitride layer and stress in the titanium nitride layer are increased by increasing kinetic energy of titanium ions which are injected into the surface of the wafer. In the method for forming titanium nitride by PVD according to the present disclosure, kinetic energy of titanium ions which are injected into the surface of the wafer is increased by controlling process parameters so that non-crystallization fraction of the titanium nitride layer and stress in the titanium nitride layer are increased.

摘要翻译： 公开了一种通过PVD形成氮化钛的方法，包括：在供给氮气和惰性气体的真空条件下通过辉光放电产生惰性气体的离子; 用氮气氮化晶片的表面和钛靶的表面; 在惰性气体的离子在电场中加速之后，用钛离子轰击钛靶的表面，从而溅射钛离子和氮化钛; 以及通过在磁场表面上沉积氮化钛而形成氮化钛层，同时将钛离子注入到晶片的表面中，使得应力被引入到氮化钛层中，其中非晶化部分 通过提高注入到晶片表面的钛离子的动能来增加氮化钛层和氮化钛层中的应力。 在根据本公开的通过PVD形成氮化钛的方法中，通过控制工艺参数来增加注入晶片表面的钛离子的动能，使得氮化钛层的非结晶部分和应力在 氮化钛层增加。

公开(公告)号：US20130020653A1

公开(公告)日：2013-01-24

申请号：US13519573

申请日：2011-08-03

申请人： Jiang Yan

发明人： Jiang Yan

IPC分类号： H01L29/06 ,  H01L27/092 ,  H01L21/302

CPC分类号： H01L21/76232

摘要： The present invention relates to a shallow trench isolation structure, manufacturing method thereof and a device based on the structure. The present invention provides a method for manufacturing a shallow trench isolation (STI) structure, characterized in comprising the following steps: providing a semiconductor substrate; forming an insulating medium on said semiconductor substrate; etching a part of the insulating medium by using a mask to expose the semiconductor substrate thereunder, the unetched insulating medium forming STI regions; and epitaxially growing a semiconductor layer on said semiconductor substrate between said STI regions as an active region. With the method provided by the present invention, the problem of filling a small-size trench is solved and the problem of STI step height is overcome.

摘要翻译： 本发明涉及一种浅沟槽隔离结构，其制造方法和基于该结构的器件。 本发明提供一种制造浅沟槽隔离（STI）结构的方法，其特征在于包括以下步骤：提供半导体衬底; 在所述半导体衬底上形成绝缘介质; 通过使用掩模蚀刻绝缘介质的一部分以暴露其下的半导体衬底，形成STI区的未蚀刻绝缘介质; 并且在所述STI区域之间的所述半导体衬底上外延生长半导体层作为有源区。 利用本发明提供的方法，解决了填充小尺寸沟槽的问题，克服了STI步长的问题。

公开(公告)号：US20120322172A1

公开(公告)日：2012-12-20

申请号：US13499288

申请日：2011-11-29

申请人： Tao Yang ,  Chao Zhao ,  Junfeng Li ,  Jiang Yan ,  Dapeng Chen

发明人： Tao Yang ,  Chao Zhao ,  Junfeng Li ,  Jiang Yan ,  Dapeng Chen

IPC分类号： H01L21/66

CPC分类号： H01L22/12 ,  H01L29/66545

摘要： The present invention discloses a method for monitoring the removal of a polycrystalline silicon dummy gate, comprising the steps of: forming a polycrystalline silicon dummy gate structure on a surface of a wafer; determining a measurement target and an error range of mass of the wafer; and measuring the mass of the wafer by a mass measurement tool after polycrystalline silicon dummy gate removal to determine whether the polycrystalline silicon dummy gate has been completely removed. According to the measurement method of the present invention, the full wafer may be quickly and accurately measured without requiring a specific test structure, to effectively monitor and determine whether the polysilicon dummy gate is thoroughly removed, meanwhile said measurement method gives feedback directly, quickly and accurately without causing any damage to the wafer.

摘要翻译： 本发明公开了一种用于监测多晶硅虚拟栅极去除的方法，包括以下步骤：在晶片的表面上形成多晶硅虚拟栅极结构; 确定晶片的测量目标和质量的误差范围; 以及通过质量测量工具在多晶硅虚拟栅极去除之后测量晶片的质量，以确定多晶硅虚拟栅极是否被完全去除。 根据本发明的测量方法，可以快速且准确地测量全晶片而不需要特定的测试结构，以有效地监测和确定多晶硅虚拟栅极是否被彻底去除，同时所述测量方法直接，快速地给出反馈， 准确地不会对晶片造成任何损坏。

公开(公告)号：US08138055B2

公开(公告)日：2012-03-20

申请号：US12850119

申请日：2010-08-04

申请人： Jin-Ping Han ,  Alois Gutmann ,  Roman Knoefler ,  Jiang Yan ,  Chris Stapelmann ,  Jingyu Lian ,  Yung Fu Chong

发明人： Jin-Ping Han ,  Alois Gutmann ,  Roman Knoefler ,  Jiang Yan ,  Chris Stapelmann ,  Jingyu Lian ,  Yung Fu Chong

IPC分类号： H01L21/336

CPC分类号： H01L21/823807 ,  H01L21/823814 ,  H01L21/823842 ,  H01L21/823864 ,  H01L29/66636 ,  H01L29/7843 ,  H01L29/7845 ,  H01L29/7848 ,  H01L2924/0002 ,  H01L2924/00

摘要： In a method of making a semiconductor device, a first gate stack is formed on a substrate at a pFET region, which includes a first gate electrode material. The source/drain regions of the substrate are etched at the pFET region and the first gate electrode material of the first gate stack is etched at the pFET region. The etching is at least partially selective against etching oxide and/or nitride materials so that the nFET region is shielded by a nitride layer (and/or a first oxide layer) and so that the spacer structure of the pFET region at least partially remains. Source/drain recesses are formed and at least part of the first gate electrode material is removed by the etching to form a gate electrode recess at the pFET region. A SiGe material is epitaxially grown in the source/drain recesses and in the gate electrode recess at the pFET region. The SMT effect is achieved from the same nitride nFETs mask.

摘要翻译： 在制造半导体器件的方法中，在包括第一栅极电极材料的pFET区域的衬底上形成第一栅极堆叠。 在pFET区域蚀刻衬底的源/漏区，并且在pFET区域蚀刻第一栅极堆叠的第一栅电极材料。 蚀刻对蚀刻氧化物和/或氮化物材料至少部分选择性，使得nFET区域被氮化物层（和/或第一氧化物层）屏蔽，并且使得pFET区域的间隔结构至少部分保留。 形成源极/漏极凹部，并且通过蚀刻去除第一栅电极材料的至少一部分，以在pFET区域形成栅电极凹部。 SiGe材料在源极/漏极凹槽中以及在pFET区域的栅极电极凹槽中外延生长。 SMT效应由相同的氮化物nFET掩模实现。

公开(公告)号：US20110006373A1

公开(公告)日：2011-01-13

申请号：US12884417

申请日：2010-09-17

申请人： Manfred Eller ,  Jiang Yan ,  Jin-Ping Han ,  Alois Gutmann

发明人： Manfred Eller ,  Jiang Yan ,  Jin-Ping Han ,  Alois Gutmann

IPC分类号： H01L27/092 ,  H01L27/088

CPC分类号： H01L21/823807 ,  H01L21/823864 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7843

摘要： Methods of fabricating transistors and semiconductor devices and structures thereof are disclosed. In one embodiment, a method of fabricating a transistor includes forming a gate dielectric over a workpiece, forming a gate over the gate dielectric, and forming a stress-inducing material over the gate, the gate dielectric, and the workpiece. Sidewall spacers are formed from the stress-inducing material on sidewalls of the gate and the gate dielectric.

摘要翻译： 公开了制造晶体管和半导体器件的方法及其结构。 在一个实施例中，制造晶体管的方法包括在工件上形成栅极电介质，在栅极电介质上形成栅极，并在栅极，栅极电介质和工件上形成应力诱发材料。 侧壁间隔物由栅极和栅极电介质的侧壁上的应力诱导材料形成。

公开(公告)号：US20080246056A1

公开(公告)日：2008-10-09

申请号：US11697806

申请日：2007-04-09

申请人： Victor W. C. Chan ,  Thomas W. Dyer ,  Sunfei Fang ,  Jinghong Li ,  Teck J. Tang ,  Henry K. Utomo ,  Jiang Yan

发明人： Victor W. C. Chan ,  Thomas W. Dyer ,  Sunfei Fang ,  Jinghong Li ,  Teck J. Tang ,  Henry K. Utomo ,  Jiang Yan

IPC分类号： H01L29/778 ,  H01L21/336

CPC分类号： H01L21/823814 ,  H01L21/823807 ,  H01L21/823864 ,  H01L29/165 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66636 ,  H01L29/7843

摘要： Methods of forming a suicide in an embedded silicon germanium (eSiGe) source/drain region using a suicide prevention spacer overlapping an interface between the eSiGe and the silicon channel, and a related PFET with an eSiGe source/drain region and a compressive stress liner in close proximity to a silicon channel thereof, are disclosed. In one embodiment, a method includes providing a gate having a nitrogen-containing spacer adjacent thereto and an epitaxially grown silicon germanium (eSiGe) region adjacent to a silicon channel of the gate; removing the nitrogen-containing spacer that does not extend over the interface between the eSiGe source/drain region and the silicon channel; forming a single silicide prevention spacer about the gate, the single silicide prevention spacer overlapping the interface; and forming the silicide in the eSiGe source/drain region using the single silicide prevention spacer to prevent the silicide from forming in at least an extension area of the silicon channel.

摘要翻译： 在嵌入式硅锗（eSiGe）源极/漏极区域中使用与eSiGe和硅沟道之间的界面重叠的防止硅化物的衬垫形成硅化物的方法以及具有eSiGe源极/漏极区域和压应力衬垫的相关PFET 公开了其接近硅通道的方式。 在一个实施例中，一种方法包括提供具有与其相邻的含氮隔离物的栅极和与栅极的硅沟道相邻的外延生长的硅锗（eSiGe）区域; 去除不在eSiGe源极/漏极区域和硅沟道之间的界面上延伸的含氮隔离物; 在栅极周围形成单个硅化物防止间隔物，单个硅化物防止间隔物与界面重叠; 以及使用单个硅化物防止间隔物在eSiGe源极/漏极区域中形成硅化物，以防止硅化物在硅沟道的至少延伸区域中形成。

公开(公告)号：US20070148921A1

公开(公告)日：2007-06-28

申请号：US11317737

申请日：2005-12-23

申请人： Jiang Yan ,  Danny Shum ,  Armin Tilke

发明人： Jiang Yan ,  Danny Shum ,  Armin Tilke

IPC分类号： H01L21/20 ,  H01L21/84 ,  H01L21/44

CPC分类号： H01L27/092 ,  H01L21/84 ,  H01L27/1203 ,  H01L27/1207

摘要： A method of making a semiconductor device begins with a semiconductor wafer that includes a first semiconductor layer overlying a second semiconductor layer. A first trench is etched in the semiconductor wafer. The first trench is filled with insulating material. A second trench is etched within the first trench and through the insulating material, such that insulating material remains along sidewalls of the first trench. The second trench exposes a portion of the second insulating layer. A semiconductor layer can then be grown within the second trench using the second semiconductor layer as a seed layer.

摘要翻译： 制造半导体器件的方法从半导体晶片开始，半导体晶片包括覆盖第二半导体层的第一半导体层。 在半导体晶片中蚀刻第一沟槽。 第一个沟槽填充绝缘材料。 在第一沟槽内蚀刻第二沟槽并穿过绝缘材料，使得绝缘材料沿着第一沟槽的侧壁保留。 第二沟槽露出第二绝缘层的一部分。 然后可以使用第二半导体层作为种子层在第二沟槽内生长半导体层。