公开(公告)号：US06816094B2

公开(公告)日：2004-11-09

申请号：US10619290

申请日：2003-07-15

申请人： Joerg Vollrath ,  Stephan Schröder

发明人： Joerg Vollrath ,  Stephan Schröder

IPC分类号： H03M900

CPC分类号： G11C7/1057 ,  G11C7/1051

摘要： A circuit configuration for the bit-parallel outputting the bits of a data word includes at least two signal lines for feeding the data signals representing the bits of the data word to driver stages and to a reference circuit. Further driver stages are connected in parallel with the driver stages and have inputs connected to the control device. The control device establishes the signal states of the data signals to be transferred on each signal line and generates a control signal depending on the type and number of the signal state changes of bit sequences to be transferred. It is possible to drive the driver stages that assigned to the signal line for which a signal state change is present.

摘要翻译： 用于比特并行输出数据字的位的电路配置包括用于将表示数据字的位的数据信号馈送到驱动器级的至少两条信号线和参考电路。 其他驱动级与驱动级并联，并具有连接到控制装置的输入。 控制装置建立要在每个信号线上传送的数据信号的信号状态，并根据要传送的位序列的信号状态变化的类型和数量产生控制信号。 可以驱动分配给信号状态改变的信号线的驱动级。

公开(公告)号：US06564346B1

公开(公告)日：2003-05-13

申请号：US09455855

申请日：1999-12-07

申请人： Joerg Vollrath ,  Ulf Lederer ,  Peter Oswald ,  Thomas Hladschik ,  Zschunke Andreas ,  Rausch Harold

发明人： Joerg Vollrath ,  Ulf Lederer ,  Peter Oswald ,  Thomas Hladschik ,  Zschunke Andreas ,  Rausch Harold

IPC分类号： G11C2900

CPC分类号： G11C29/72 ,  G01R31/31935 ,  G11C29/56

摘要： A method for providing a compressed bit fail map, in accordance with the invention includes the steps of testing a semiconductor device to determine failed devices and transferring failure information to display a compressed bit map by designating areas of the bit map for corresponding failure locations on the semiconductor device. Failure classification is provided by designating shapes and dimensions of fail areas in the designated areas of the bit map such that the fail area shapes and dimensions indicate a fail type.

摘要翻译： 根据本发明的用于提供压缩比特失败映射的方法包括以下步骤：测试半导体器件以确定故障设备并传送故障信息以显示压缩位图，通过指定位图上的相应故障位置的区域 半导体器件。 通过在位图的指定区域中指定失效区域的形状和尺寸来提供故障分类，使得故障区域形状和尺寸表示故障类型。

公开(公告)号：US06453433B1

公开(公告)日：2002-09-17

申请号：US09281021

申请日：1999-03-30

申请人： Joerg Vollrath

发明人： Joerg Vollrath

IPC分类号： G11C2900

CPC分类号： G11C29/028 ,  G11C11/401 ,  G11C29/02 ,  G11C29/50 ,  G11C2029/5004

摘要： Disclosed is a method and apparatus for testing a semiconductor memory having a plurality of memory cells arranged in rows and columns and a plurality of sense amplifiers, each for amplifying memory cell signals of a common row or column. In an illustrative embodiment of the method, a voltage level or test pattern is written into at least one target cell of the memory cells. A word line coupled to the target cell is then activated and subsequently deactivated, to thereby modify the voltage level stored in the cell, while the associated sense amplifier is prevented from refreshing the cell as the word line is activated, e.g., by disabling the sense amplifier. A test bit line voltage is then applied to a bit line coupled to the cell to charge the same. Data is then read from the target cell with settings of the associated sense amplifier enabled, and compared to the original voltage level written into the cell. The process is repeated for different test bit line voltages. The method can be used to determine the signals at the sense amplifiers during normal operation of the memory, without employing complex and costly picoprobes.

摘要翻译： 公开了一种用于测试半导体存储器的方法和装置，该半导体存储器具有排列成行和列的多个存储单元和多个读出放大器，每个用于放大公共行或列的存储单元信号。 在该方法的说明性实施例中，将电压电平或测试图案写入存储器单元的至少一个目标单元。 然后，耦合到目标单元的字线被激活并且随后被去激活，从而修改存储在单元中的电压电平，同时当字线被激活时防止相关的读出放大器刷新单元，例如通过禁用该感测 放大器 然后将测试位线电压施加到耦合到该单元的位线以对其进行充电。 然后从相关读出放大器的设置使能的目标单元读取数据，并将其与写入单元的原始电压电平进行比较。 针对不同的测试位线电压重复该过程。 该方法可用于在存储器的正常操作期间确定读出放大器处的信号，而不需要使用复杂和昂贵的皮秒。

公开(公告)号：US07719868B2

公开(公告)日：2010-05-18

申请号：US11715839

申请日：2007-03-08

申请人： Joerg Vollrath

发明人： Joerg Vollrath

IPC分类号： G11C5/06

CPC分类号： G11C5/063 ,  G11C7/18 ,  G11C11/4097 ,  H01L27/10885 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated semiconductor memory has memory cells, with at least one pair of bit lines which comprises a first bit line and a second bit line, and with at least one sense amplifier which has the first bit line and the second bit line connected to it. The bit lines respectively have a first conductor track structure and a second conductor track structure, where the memory cells are respectively connected to the second conductor track structure, and where the first conductor track structure is respectively interposed between the sense amplifier and the second conductor track structure of the respective bit line and is arranged at a greater distance from the substrate area than the respective second conductor track structure.

摘要翻译： 集成半导体存储器具有存储单元，其中至少一对位线包括第一位线和第二位线，以及至少一个读出放大器，其具有与其连接的第一位线和第二位线。 位线分别具有第一导体轨道结构和第二导体轨道结构，其中存储单元分别连接到第二导体轨道结构，并且其中第一导体轨道结构分别插入在读出放大器和第二导体轨道之间 相对于位线的结构，并且布置在距离基板区域比相应的第二导体轨道结构更远的距离处。

公开(公告)号：US20100039845A1

公开(公告)日：2010-02-18

申请号：US12193267

申请日：2008-08-18

申请人： Joerg Vollrath ,  Marcin Gnat

发明人： Joerg Vollrath ,  Marcin Gnat

IPC分类号： G11C5/02 ,  G11C5/06 ,  G11C11/24 ,  G11C7/06

CPC分类号： G11C7/18 ,  G11C5/063 ,  G11C7/02 ,  G11C11/4097 ,  H01L27/0207 ,  H01L27/10885

摘要： An integrated circuit includes a memory cell array including a plurality of memory cells. A first plurality of bit lines is positioned in a first plane. The first plurality of bit lines is electrically coupled to a first set of the memory cells. A second plurality of bit lines is positioned in a second plane that is different than the first plane. The second plurality of bit lines is electrically coupled to a second set of the memory cells.

摘要翻译： 集成电路包括包括多个存储单元的存储单元阵列。 第一多个位线位于第一平面中。 第一组多个位线电耦合到第一组存储器单元。 第二多个位线位于与第一平面不同的第二平面中。 第二组多个位线电耦合到第二组存储器单元。

公开(公告)号：US07372095B2

公开(公告)日：2008-05-13

申请号：US11213342

申请日：2005-08-26

申请人： Joerg Vollrath

发明人： Joerg Vollrath

IPC分类号： H01L29/76 ,  H01L29/788

CPC分类号： H01L27/11568 ,  H01L27/115 ,  H01L29/66833

摘要： An integrated semiconductor circuit includes a transistor and a strip conductor (11). The transistor includes a first (1) and a second source/drain region (2) and a gate electrode. The strip conductor (11) is electrically insulated from a semiconductor body at least by a gate dielectric and forms the gate electrode in the area of the transistor. The strip conductor (11) extends along a first direction (x) in the area of the transistor. The second source/drain region (2) is arranged offset with respect to the first source/drain region (1) in the first direction (x). The transistor thus formed has an inversion channel (K1) that only extends between two corner areas (1a, 2a) facing one another of the first and of the second source/drain region, i.e. is much narrower than in the case of a conventional transistor.

摘要翻译： 集成半导体电路包括晶体管和带状导体（11）。 晶体管包括第一（1）和第二源/漏区（2）和栅电极。 带状导体（11）至少通过栅极电介质与半导体本体电绝缘，并在晶体管的区域中形成栅电极。 带状导体（11）沿着晶体管的区域中的第一方向（x）延伸。 第二源极/漏极区域（2）在第一方向（x）上相对于第一源极/漏极区域（1）偏移地布置。 这样形成的晶体管具有仅在第一和第二源极/漏极区域彼此面对的两个拐角区域（1a，2a）之间延伸的反转沟道（K 1），即比在 常规晶体管。

公开(公告)号：US07224627B2

公开(公告)日：2007-05-29

申请号：US11100617

申请日：2005-04-07

申请人： Marcin Gnat ,  Aurel von Campenhausen ,  Joerg Vollrath ,  Ralf Schneider

发明人： Marcin Gnat ,  Aurel von Campenhausen ,  Joerg Vollrath ,  Ralf Schneider

IPC分类号： G11C7/00

CPC分类号： G11C29/12005 ,  G11C29/12

摘要： Integrated semiconductor circuits, in particular, dynamic random access memories include a multiplicity of generator circuits for generating internal voltage levels from an externally applied supply voltage. During testing, the internal voltage levels are altered by the output voltage generated at the output of the generator circuit being adapted to an externally applied test voltage. If the test voltage is outside a tolerance range, the semiconductor circuit maybe destroyed. A protection circuit connected in parallel with the generator circuit limits the output voltage.

摘要翻译： 集成半导体电路，特别是动态随机存取存储器包括用于从外部施加的电源电压产生内部电压电平的多个发生器电路。 在测试期间，内部电压电平由发生器电路输出端产生的输出电压改变为外部施加的测试电压。 如果测试电压超出公差范围，则半导体电路可能被破坏。 与发生器电路并联连接的保护电路限制输出电压。

公开(公告)号：US06998664B2

公开(公告)日：2006-02-14

申请号：US10787119

申请日：2004-02-27

申请人： Joerg Vollrath ,  Stephan Schröder ,  Tobias Hartner

发明人： Joerg Vollrath ,  Stephan Schröder ,  Tobias Hartner

IPC分类号： H01L27/108 ,  H01L29/76

CPC分类号： H01L27/10885 ,  H01L27/10888 ,  H01L27/10891

摘要： An integrated semiconductor circuit includes a cell array having memory cells which can be read by word lines and bit lines. Two bit lines in each case are connected to inputs of the same signal amplifier. In order to compensate for parasitic capacitances which arise at thin sidewall insulations between the patterned word lines and adjacent bit line contacts which connect the bit lines located at a higher level to the active regions located at a deeper level, two additional word lines and dummy contacts of the bit lines are dummy contacts lead past this additional word lines. The additional parasitic capacitances produced by the dummy contacts alter the electrical potential of the respective reference bit line at the signal amplifier in the same way as the parasitic capacitances of activated bit lines, as a result of which the measured differential potential is corrected with respect to the parasitic effects.

摘要翻译： 集成半导体电路包括具有可由字线和位线读取的存储单元的单元阵列。 每种情况下的两个位线连接到相同信号放大器的输入。 为了补偿在图案化字线和相邻位线触点之间的薄侧壁绝缘处产生的寄生电容，其将位于较高电平的位线连接到位于较深电平的有源区，两个附加字线和虚拟触点 的位线是虚拟触点通过这个附加字线。 由虚拟触点产生的附加寄生电容以与激活的位线的寄生电容相同的方式改变信号放大器处的各个参考位线的电位，结果是相对于 寄生效应。

公开(公告)号：US20050289413A1

公开(公告)日：2005-12-29

申请号：US11145192

申请日：2005-06-06

申请人： Joerg Vollrath ,  Marcin Gnat ,  Aurel Campenhausen ,  Frank Schroeppel

发明人： Joerg Vollrath ,  Marcin Gnat ,  Aurel Campenhausen ,  Frank Schroeppel

IPC分类号： G11B20/00 ,  G11B20/18 ,  G11B27/36 ,  G11C29/00 ,  G11C29/14 ,  G11C29/38

CPC分类号： G11C29/1201 ,  G11C29/14 ,  G11C29/38

摘要： An integrated semiconductor memory includes memory cells that store a first data record has at least one datum with a first or second data value and a second data record has at least one datum with the first or second data value. The integrated semiconductor memory has a combination circuit that generates the third data record on the output side from the data records fed to the combination circuit on the input side to ascertain based on the third data record whether the first and second data records have been fed to the combination circuit on the input side. The combination circuit generates the datum of the third data record with the first data value, if the first and second data records were fed to the combination circuit on the input side.

摘要翻译： 集成半导体存储器包括存储第一数据记录的存储器单元具有至少一个具有第一或第二数据值的数据，而第二数据记录具有至少一个具有第一或第二数据值的数据。 集成半导体存储器具有组合电路，其从在输入侧馈送到组合电路的数据记录在输出侧产生第三数据记录，以基于第三数据记录来确定第一和第二数据记录是否被馈送到 输入侧的组合电路。 如果第一和第二数据记录被馈送到输入侧的组合电路，则组合电路产生具有第一数据值的第三数据记录的数据。

公开(公告)号：US20050218960A1

公开(公告)日：2005-10-06

申请号：US11092963

申请日：2005-03-30

申请人： Aurel Campenhausen ,  Joerg Vollrath ,  Ralf Schneider ,  Marcin Gnat

发明人： Aurel Campenhausen ,  Joerg Vollrath ,  Ralf Schneider ,  Marcin Gnat

IPC分类号： B60T8/34 ,  G01R31/27 ,  G01R31/28 ,  G11C29/48 ,  G11C29/50

CPC分类号： G11C29/1201 ,  G01R31/275 ,  G01R31/2884 ,  G11C29/48 ,  G11C29/50 ,  G11C2029/5002

摘要： An integrated circuit includes a circuit component, a first control circuit and a switchable resistance network. An input voltage is fed to the circuit component on the input side. A control signal generated by the first control circuit is fed to the control terminal of the circuit component. With the switchable resistance network, the first resistance or the second resistance is connected between an output terminal of the circuit component and the output terminal of the integrated circuit to generate a voltage drop between the input side and the output terminal of the circuit component. The integrated circuit makes it possible to generate a current at the output terminal of the circuit component in a manner dependent on the control signal and the voltage dropped between the input side and the output terminal of the circuit component. Families of characteristic curves of transistors of an integrated circuit are determined by the integrated circuit.

摘要翻译： 集成电路包括电路部件，第一控制电路和可切换电阻网络。 输入电压被馈送到输入侧的电路部件。 由第一控制电路产生的控制信号被馈送到电路部件的控制端。 利用可切换电阻网络，第一电阻或第二电阻连接在电路部件的输出端和集成电路的输出端之间，以在电路部件的输入侧和输出端之间产生电压降。 集成电路使得可以以取决于控制信号的方式在电路部件的输出端产生电流以及在电路部件的输入侧和输出端子之间落下的电压。 集成电路的晶体管的特性曲线族由集成电路确定。