公开(公告)号：US4849759A

公开(公告)日：1989-07-18

申请号：US136031

申请日：1987-12-21

申请人： John B. Hughes

发明人： John B. Hughes

IPC分类号： H03M1/38 ,  H03M1/00 ,  H03M1/10 ,  H03M1/14

CPC分类号： H03M1/0607 ,  H03M1/162 ,  H03M1/167

摘要： In a half-flash analogue to digital converter (ADC) for balanced signals, d.c. offset compensation is provided by means of two negative feedback arrangements 510 and 520. A first compensating signal LOFF is the time-average of the output of the middle comparator MC17 of the coarse converter stage and provides compensation of offsets in the most significant bits (MSB) of the output. A second compensating signal COFF is generated by an additional comparator MC34 to effect compensation of offsets re-introduced when a difference amplifier 404 forms the residual signal V.sub.LSB for the input to the fine converter stage.

公开(公告)号：US4354274A

公开(公告)日：1982-10-12

申请号：US194508

申请日：1980-10-06

申请人： John B. Hughes

发明人： John B. Hughes

IPC分类号： H03D13/00 ,  H04L7/033 ,  H03D3/24

CPC分类号： H03D13/00 ,  H04L7/033

摘要： A digital signal transmission system in which a pulse code modulated (PCM) signal is retimed in a regenerator using a decision circuit supplied by a clock, the frequency of which is half that of the bit rate (typically 1 Gigabit/second), and is demultiplexed using multiplexers clocked at a frequency half that of the bit rate. In each case the clock frequency is derived from the data stream using a clock extractor. A voltage controlled oscillator (VCO) generating a signal at substantially half the bit rate is connected to one input of a phase detector to another input of which is connected to receive current pulses representing transitions in the incoming data signal. The phase detector comprises first, second and third pairs of long tailed-pair connected transistors, the collectors of the transistors of the first pair of being connected respectively to the common connected transistors of second and third pairs. A first delay circuit providing a delay of approximately a quarter of a period of the VCO is connected between the base electrode of one of the first pair of transistors and the base electrode of one transistor of each of the second and third pairs of transistors. A second delay circuit of the same period as the first delay circuit is connected between the base electrode of the other of the first pair of transistors and the base electrode of the other transistor of each of the second and third pairs of transistors.

摘要翻译： 一种数字信号传输系统，其中脉冲编码调制（PCM）信号使用由时钟提供的判定电路在再生器中重新定时，其频率是比特率（通常为1千兆/秒）的一半，并且是 使用以比特率的一半频率计时的多路复用器解复用。 在每种情况下，使用时钟提取器从数据流导出时钟频率。 产生基本上一半比特率的信号的压控振荡器（VCO）被连接到相位检测器的一个输入，其另一个输入被连接以接收表示输入数据信号中的跳变的电流脉冲。 相位检测器包括第一对，第二和第三对长尾对连接的晶体管，第一对晶体管的集电极分别连接到第二和第三对的公共连接的晶体管。 提供VCO周期约四分之一延迟的第一延迟电路连接在第一对晶体管之一的基极和第二和第三对晶体管中的每个晶体管的一个晶体管的基极之间。 与第一延迟电路相同的周期的第二延迟电路连接在第一对晶体管的另一个的基极和第二和第三对晶体管中的每一个的另一晶体管的基极之间。

公开(公告)号：US07265609B2

公开(公告)日：2007-09-04

申请号：US10557346

申请日：2004-05-14

申请人： John B. Hughes

发明人： John B. Hughes

IPC分类号： H03K5/00

CPC分类号： H03F3/45991 ,  H03F2200/294 ,  H03F2200/372 ,  H03H11/0444 ,  H03H11/08

摘要： A transconductor circuit, such as a gyrator filter, comprises an arrangement of balanced class AB transconductors, capacitors and floating MOS resistors formed by MOS transistors operating in their triode region. Tuning of the filter is effected by varying a common supply rail voltage. The circuit includes a means for producing a voltage offset from the common mode voltage of the class AB transconductors. The offset voltage is supplied to a parallel arrangement of a class AB transconductor having a transconductance and the source-drain path of a MOS transistor emulating a MOS resistor. The current output of the parallel arrangement is integrated and supplied as a control voltage to the gate electrode of the MOS transistor. By loop action the control voltage is adjusted and supplied to the floating MOS resistors.

摘要翻译： 诸如回转器滤波器的跨导电路包括平衡AB类跨导体，电容器和由其三极管区域中工作的MOS晶体管形成的浮动MOS电阻器的布置。 滤波器的调谐通过改变共同的电源轨电压来实现。 该电路包括用于产生与AB类跨导体的共模电压的偏移电压的装置。 偏移电压被提供给具有跨导的AB类跨导体并且模拟MOS电阻的MOS晶体管的源极 - 漏极路径的并联布置。 并联装置的电流输出被集成并作为控制电压提供给MOS晶体管的栅电极。 通过循环动作，控制电压被调整并提供给浮动MOS电阻。

公开(公告)号：US07106106B2

公开(公告)日：2006-09-12

申请号：US10515688

申请日：2003-05-21

申请人： John B. Hughes

发明人： John B. Hughes

IPC分类号： H03K5/22

CPC分类号： H03K3/356191 ,  H03K3/356156

摘要： A comparator is provided that compares one or more input signals in a regenerative circuit. One or more switched isolate the signal inputs after regeneration has started but before regeneration has reached such an extent that large voltage swings in the regeneration circuit are transmitted back to the signal source and corrupt the signal source or neighboring circuits. Furthermore, as controlled by a control circuit, the instant of isolating the signal source can be dependent on the degree of regeneration such as being dependent on a predetermined degree of regeneration. The comparator may be incorporated in an electronic device such as an analog-to-digital converter or a wireless receiver or transceiver.

摘要翻译： 提供了比较器，其比较再生电路中的一个或多个输入信号。 一个或多个切换隔离了再生已经开始之后的信号输入，但是在再生达到这样的程度之后，再生电路中的大电压摆动被传送回信号源并损坏信号源或相邻电路。 此外，由控制电路控制，隔离信号源的时刻可以取决于再生程度，例如取决于预定的再生程度。 比较器可以并入诸如模数转换器或无线接收器或收发器的电子设备中。

公开(公告)号：US5473275A

公开(公告)日：1995-12-05

申请号：US302580

申请日：1994-09-08

申请人： John B. Hughes ,  Kenneth W. Moulding

发明人： John B. Hughes ,  Kenneth W. Moulding

IPC分类号： G06G7/186 ,  G06G7/64

CPC分类号： G06G7/1865

摘要： A switched current bilinear integrator comprising interconnected current memory cells (M1, M2) in which, during a first phase of a clock cycle, an input current is fed to the inputs of the current memory cells and during a second phase of the clock cycle an inverted version (A1) of the input current is fed to the inputs of the current memory cells. The output of the integrator is obtained by combining the output (optionally scaled) of the first current memory cell (M1) with an inverted (A2) version of the output (optionally scaled) of the second memory cell (M2). A lossy integrator may be formed by feeding back to the input a scaled version of the current stored in the second current memory cell and an inverted, scaled version of the current stored in the first memoy cell.

摘要翻译： 一种开关电流双线性积分器，包括互连的当前存储单元（M1，M2），其中在时钟周期的第一阶段期间，输入电流被馈送到当前存储器单元的输入端，并且在时钟周期的第二阶段期间 输入电流的反相（A1）馈送到当前存储单元的输入。 通过将第一当前存储器单元（M1）的输出（可选地缩放）与第二存储器单元（M2）的输出（可选地缩放）的反相（A2）版本组合来获得积分器的输出。 可以通过将存储在第二当前存储器单元中的电流的缩放版本和存储在第一memoy单元中的电流的反转缩放版本反馈给输入来形成有损积分器。

公开(公告)号：US5400273A

公开(公告)日：1995-03-21

申请号：US186397

申请日：1994-01-25

申请人： John B. Hughes ,  Kenneth W. Moulding

发明人： John B. Hughes ,  Kenneth W. Moulding

IPC分类号： G11C27/00 ,  G11C27/02 ,  G11C13/00

CPC分类号： G11C27/028

摘要： An analogue current memory arrangement includes an input (30) and an output (33). A first (coarse) current memory cell (T31,S31,C31) senses the input current during clock phase .phi.1a and reproduces the sensed current during clock phases .phi.1b and .phi.2. A second (fine) current memory cell (T32,C32,S32) acts as a current source during phase .phi.1a when a reference voltage (VR) is applied to the gate of transistor (T32). The second current memory cell senses the difference between the input current and the output of the first current memry cell during phase .phi.1b and reproduces the sensed current during phase .phi.2.During phase .phi.2 the input switch (S30) is opened and the output switch (S34) is closed causing the combined outputs of the first and second current memory cells to be fed to the output (33).(FIGS. 3 and 4).

摘要翻译： 模拟电流存储装置包括输入端（30）和输出端（33）。 第一（粗）当前存储单元（T31，S31，C31）在时钟相位phi 1a期间检测输入电流，并且在时钟相位phi 1b和phi 2期间再现感测的电流。第二（精细）当前存储单元（T32，C32 ，S32）在将参考电压（VR）施加到晶体管（T32）的栅极时用作相位phi 1a期间的电流源。 第二当前存储单元感测在相位phi 1b期间输入电流和第一电流存储单元的输出之间的差异，并且在相位phi2期间再现感测的电流。在相位phi 2期间，输入开关（S30）被打开，输出 开关（S34）闭合，使得第一和第二当前存储单元的组合输出被馈送到输出端（33）。 （图3和图4）。

公开(公告)号：US5179301A

公开(公告)日：1993-01-12

申请号：US574622

申请日：1990-08-28

申请人： John B. Hughes

发明人： John B. Hughes

IPC分类号： G06G7/18 ,  G06G7/184

CPC分类号： G06G7/184

摘要： A differentiator circuit for sampled analog input currents comprises a first current memory cell including a capacitor (C2), a switch (S2), a transistor (T2) and a transistor (T3) and a second current memory cell including a capacitor (C1), a switch (S1) and a transistor (T1). During one portion (.phi.1) of each sampling period the input current (i) minus the current produced by the transistor (T1), which acts as a current source when switch (S1) is open, together with appropriate bias currents to allow bi-directional input currents to be handled, is fed via a switch (S3) to the first current memory cell. During another portion (.phi.2) of each sampling period the input current plus an appropriate bias current is fed to the input of the second current memory cell. The switches (S3) and (S2) are open so transistor (T2) acts as a current source providing an output via switch (S4) at an output (17) in addition to the output (15). The differentiated output signal is available throughout at output (15) but only during the other portion (.phi.2) of each sampling period at output (17). The circuit corresponds to a backward Euler mapping from continuous time ideal differentiators. Corresponding circuits giving foward Euler and bilinear mappings are also disclosed as are circuits for lossy differentiators. Various alternative current memory cells are disclosed.

公开(公告)号：US5063342A

公开(公告)日：1991-11-05

申请号：US401729

申请日：1989-08-31

申请人： John B. Hughes ,  Kenneth W. Moulding

发明人： John B. Hughes ,  Kenneth W. Moulding

IPC分类号： G01K3/00 ,  G01K7/01

CPC分类号： G01K3/005 ,  G01K7/01 ,  Y10S323/907

摘要： An integrated temperature threshold sensing circuit comprises first and second bipolar transistors (Q1, Q2) biased so that the current density in the first transistor is larger than that in the second transistor by a first known factor. The first and second transistors have their collectors and bases connected to a first bias voltage source and to a second bias voltage source, respectively, and their emitters connected respectively to first and second current sources (12,14) for passing first and second bias currents (I.sub.1, I.sub.2) of known relative proportions (K:1) through the respective first and second transistors. A voltage comparator (26) is arranged to compare a first predetermined fraction (R(R+r)) of the base-emitter voltage of the first transistor (Q1) with a second, larger predetermined fraction (1) of the base-emitter voltage of the second transistor (Q2) so that an output (28) of the comparator assumes a first state when the temperature of the two devices is above a known threshold temperature and assumes a second state when the temperature of the two devices is below the known threshold temperature. The circuit is accurate and is compatible with MOS technology.

公开(公告)号：US5021692A

公开(公告)日：1991-06-04

申请号：US446518

申请日：1989-12-04

申请人： John B. Hughes

发明人： John B. Hughes

IPC分类号： G06G7/184 ,  G11C27/02

CPC分类号： G06G7/184 ,  G11C27/028

摘要： A bilinear integrator circuit includes a first input (1) and a second input (5) with the first input connected to the input of a first current memory cell formed by two transistors (T1, T2), a capacitor (C1), and a switch (S1). The first current memory cell is arranged to store a current applied to its input during a first portion .phi. of each sampling period and to reproduce that current at its output during a second portion .phi. of the succeeding sampling period. The second input is connected via a further switch (S2) to the input of a second current memory cell formed by three transistors (T3, T4 and T5), capacitor (C2) and a switch (S3). During a second portion .phi. of each sampling period the current applied to the second input and the current produced at the output of the first current memory cell are applied to the input of the second current memory cell. The second current memory cell has two outputs (from the drain electrodes of transistors T4, T5). The first output (from T4) is fed back to the input of the first current memory cell while the second output (at T5) is coupled to the integrator output (8).

公开(公告)号：US4958123A

公开(公告)日：1990-09-18

申请号：US286600

申请日：1988-12-16

申请人： John B. Hughes

发明人： John B. Hughes

IPC分类号： H03H19/00 ,  G11C27/02

CPC分类号： G11C27/028 ,  G11C27/02

摘要： A circuit arrangement for processing sampled analog electrical signals, each sample being in the form of a current, includes apparatus for combining, in predetermined proportions, the input sample current in a present sample period with current(s) derived from input sample current(s) in one or more preceding sample periods. Apparatus is also provided for deriving the processed output signal from the combined current produced by the combining apparatus in successive sample periods. The circuit arrangement is formed by a plurality of circuit modules, for example, scaling, memory, and integrator modules, each of which may be capable of processing only unidirectional currents. To enable easy interconnection of the modules, each module is arranged to receive and deliver unidirection currents and to generate internally bias currents to enable conversion from bidirectional to unidirectional currents and vice versa.