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    Redundant circuit for memory device
    32.
    发明授权
    Redundant circuit for memory device 有权
    存储器冗余电路

    公开(公告)号：US06480428B2

    公开(公告)日：2002-11-12

    申请号：US09740712

    申请日：2000-12-19

    申请人： Hua Zheng ,  Jae-Hyeong Kim

    发明人： Hua Zheng ,  Jae-Hyeong Kim

    IPC分类号： G11C700

    CPC分类号： G11C29/785 ,  G11C17/18

    摘要： A redundant circuit that includes a combination of fuses and anti-fuses, and which may be used during various phases of the manufacturing process (e.g., during wafer test or final test) to replace a defective circuit. The redundant circuit includes (1) a replacement circuit (e.g., a redundant memory cell) that is configurable to replace a defective circuit, and (2) supporting circuitry for the replacement circuit. The support circuit is configurable to provide a control signal (e.g., to activate a word line) for the replacement circuit and further includes at least one fuse and at least one anti-fuse. The fuses or anti-fuses may be programmed to provide a programmed value (e.g., a programmed address) for the replacement circuit. The redundant circuit can be efficiently fabricated within a memory device, and may also be used for other circuits and applications.

    摘要翻译： 包括熔丝和抗熔丝的组合的冗余电路，并且其可以在制造过程的各个阶段（例如在晶片测试或最终测试期间）中使用以替换有缺陷的电路。 冗余电路包括（1）可配置以替换有缺陷的电路的替换电路（例如，冗余存储单元），和（2）用于替换电路的支持电路。 支持电路可配置为为替换电路提供控制信号（例如，激活字线），并且还包括至少一个熔丝和至少一个反熔丝。 保险丝或反熔丝可以被编程为为替换电路提供编程值（例如，编程地址）。 冗余电路可以有效地制造在存储器件中，并且也可以用于其它电路和应用。

    Memory array architecture supporting block write operation
    33.
    发明授权
    Memory array architecture supporting block write operation 有权
    内存阵列架构支持块写操作

    公开(公告)号：US06457094B2

    公开(公告)日：2002-09-24

    申请号：US09235222

    申请日：1999-01-22

    申请人： Hua Zheng

    发明人： Hua Zheng

    IPC分类号： G06F1200

    CPC分类号： G11C7/1096 ,  G11C7/1048 ,  G11C7/1078

    摘要： A memory array architecture that supports block write operation and has many advantages over conventional memory array architectures. A memory array is partitioned into a number of (N) segments. Each segment includes at least one bit line. Each segment is associated with a local input/output (I/O) line that couples to zero or more bit lines within that segment. The bit lines are coupled to the local I/O line by controlling one or more column select lines associated with that segment. Each segment is also associated with a write driver that couples to the local I/O line. Each local I/O line has a length that is a portion of a length of the memory array. A block write operation is performed by concurrently driving one or more write drivers (up to N write drivers). Each write driver drives the bit lines coupled to the local I/O line associated with that write driver.

    摘要翻译： 支持块写入操作的存储器阵列架构，并且与传统的存储器阵列架构相比具有许多优点。 存储器阵列被划分成多个（N）段。 每个段包括至少一个位线。 每个段与本地输入/输出（I / O）线相关联，该线连接到该段内的零位或更多位线。 位线通过控制与该段相关联的一个或多个列选择线来耦合到本地I / O线。 每个段也与耦合到本地I / O线的写入驱动器相关联。 每个本地I / O线的长度是存储器阵列长度的一部分。 通过同时驱动一个或多个写入驱动器（最多N个写入驱动器）执行块写入操作。 每个写入驱动器驱动耦合到与该写入驱动器相关联的本地I / O线的位线。

    Circuit and a method for configuring pad connections in an integrated device
    34.
    发明授权
    Circuit and a method for configuring pad connections in an integrated device 有权
    电路和在集成器件中配置焊盘连接的方法

    公开(公告)号：US06204072B1

    公开(公告)日：2001-03-20

    申请号：US09417029

    申请日：1999-10-12

    申请人： Jeffrey P. Wright ,  Hua Zheng

    发明人： Jeffrey P. Wright ,  Hua Zheng

    IPC分类号： H01L2166

    CPC分类号： G01R31/2648 ,  G01R31/318505 ,  G01R31/318511 ,  G01R31/31905

    摘要： An integrated device includes a configuration circuit that is coupled to first and second bond pads and first and second conductive paths of the integrated device. The circuit receives a map signal that has a first value during a first operational mode of the integrated device and a second value during a second operational mode of the integrated device. In response to the first value, the circuit couples the first pad to the second conductive path. In response to the second value, the circuit couples the first pad to the first conductive path and the second pad to the second conductive path. The first operational mode may be a wafer test mode.

    摘要翻译： 集成器件包括耦合到第一和第二接合焊盘以及集成器件的第一和第二导电通路的配置电路。 电路在集成装置的第一操作模式期间接收具有第一值的地图信号，并且在集成装置的第二操作模式期间接收第二值。 响应于第一值，电路将第一焊盘耦合到第二导电路径。 响应于第二值，电路将第一焊盘耦合到第一导电路径，将第二焊盘耦合到第二导电路径。 第一操作模式可以是晶片测试模式。

    Method and apparatus for controlling the operation of an integrated circuit responsive to out-of-synchronism control signals
    36.
    发明授权
    Method and apparatus for controlling the operation of an integrated circuit responsive to out-of-synchronism control signals 有权
    响应于不同步控制信号来控制集成电路的操作的方法和装置

    公开(公告)号：US6141290A

    公开(公告)日：2000-10-31

    申请号：US291414

    申请日：1999-04-13

    申请人： Timothy B. Cowles ,  Jeffrey P. Wright ,  Hua Zheng

    发明人： Timothy B. Cowles ,  Jeffrey P. Wright ,  Hua Zheng

    IPC分类号： G11C11/406 ,  G11C8/00

    CPC分类号： G11C11/406

    摘要： A self refresh decoder generates a self refresh command as long as the clock enable signal transitions low within a predetermined latency period after an auto refresh command is generated. As a result, an SDRAM is able to enter the self refresh mode even though the clock enable control signal differentiating the auto refresh command from the self refresh command is excessively delayed beyond the other control signals corresponding to both the auto refresh and the self refresh commands. The self refresh decoder includes a counter that is preloaded with a latency value and decrements to a terminal count responsive to the auto refresh command to terminate the latency period. The output of the counter is decoded to provide an enable signal as long as the terminal count has not been reached. As long as the enable signal is present, the self refresh command is generated responsive to receipt of the clock enable signal.

    摘要翻译： 只要在生成自动刷新命令之后的预定等待时间段内，自刷新解码器产生自刷新命令，只要时钟使能信号变为低电平即可。 结果，即使将与自刷新命令相区别的自动刷新命令的时钟使能控制信号被过度延迟超过对应于自刷新命令和自刷新命令的其他控制信号，SDRAM也能够进入自刷新模式 。 自刷新解码器包括预先加载等待时间值的计数器，并且响应于自动刷新命令而减小到终端计数以终止等待时间。 只要终端计数未达到，计数器的输出被解码以提供使能信号。 只要存在使能信号，响应于接收到时钟使能信号而产生自刷新命令。

    Low word line to bit line short circuit standby current semiconductor memory
    37.
    发明授权
    Low word line to bit line short circuit standby current semiconductor memory 失效
    低字线到位线短路待机电流半导体存储器

    公开(公告)号：US06046948A

    公开(公告)日：2000-04-04

    申请号：US114600

    申请日：1998-07-14

    申请人： Hua Zheng ,  Yuan-Mou Su

    发明人： Hua Zheng ,  Yuan-Mou Su

    IPC分类号： G11C7/12 ,  G11C8/08 ,  G11C11/408 ,  G11C11/4094 ,  G11C13/00

    CPC分类号： G11C7/12 ,  G11C11/4085 ,  G11C11/4094 ,  G11C8/08

    摘要： A precharge circuit is operable during a standby mode to drive a word line to a low voltage level and one or more (pairs of) bit lines to a standby voltage level. The precharge circuit comprises a driver for driving the on or more bit lines to the stand by voltage level. The precharge circuit also includes a control circuit connected to a control input of the driver which control circuit receives the standby signal. The control circuit outputs a varying enable signal to the driver for varying the drive of the bit lines by the driver. The precharge circuit can include a first current limiting driver for driving the bit lines to the standby voltage level, and second driver, for driving the bit lines to the standby voltage level. The second driver has a greater switching speed, and a higher current driving capacity, than the first current limiting driver. Tie control circuit enables the second driver for a certain period of time in response to detecting an indication of a beginning of the standby mode of the standby signal.

    摘要翻译： 预充电电路在待机模式期间可操作以将字线驱动到低电压电平和一个或多个（对）位线到待机电压电平。 预充电电路包括用于通过电压电平驱动一个或多个位线到支架的驱动器。 预充电电路还包括连接到驱动器的控制输入端的控制电路，该控制电路接收待机信号。 控制电路向驾驶员输出变化的使能信号，以改变驾驶员对位线的驱动。 预充电电路可以包括用于将位线驱动到待机电压电平的第一限流驱动器和用于将位线驱动到待机电压电平的第二驱动器。 第二个驱动器具有比第一个限流驱动器更大的开关速度和更高的电流驱动能力。 响应于检测到待机信号的待机模式的开始的指示，带状控制电路使得第二驱动器能够持续一段时间。

    Memory device output circuit having multiple operating modes
    39.
    发明授权
    Memory device output circuit having multiple operating modes 有权
    存储器件输出电路具有多种工作模式

    公开(公告)号：US5986945A

    公开(公告)日：1999-11-16

    申请号：US294852

    申请日：1999-04-20

    申请人： Hua Zheng

    发明人： Hua Zheng

    IPC分类号： G11C7/10 ,  G11C7/22 ,  G11C7/04

    CPC分类号： G11C7/106 ,  G11C7/1051 ,  G11C7/22

    摘要： A memory device that includes decoding circuitry, a memory array, conditioning circuitry, and an output circuit. The decoding circuitry is configured to receive address information and generate a set of control signals. The memory array couples to the decoding circuitry and is configured to provide a data value in response to the set of control signals. The conditioning circuitry couples to the memory array and is configured to receive and condition the data value to provide a data bit. The output circuit couples to the conditioning circuitry and is configured to receive the data bit and provide an output bit. The output circuit is further configured to operate in one of a number of operating modes, with each operating mode corresponding to a different timing scheme. The output circuit can be implemented using a pair of latches coupled in series. The different operating modes can be achieved, for example, by selectively placing one of the latches in a bypass mode. A timing circuit can be used to provide the necessary clock signal(s) for the output circuit.

    摘要翻译： 一种包括解码电路，存储器阵列，调节电路和输出电路的存储器件。 解码电路被配置为接收地址信息并产生一组控制信号。 存储器阵列耦合到解码电路，并且被配置为响应于该组控制信号来提供数据值。 调理电路耦合到存储器阵列并被配置为接收和调节数据值以提供数据位。 输出电路耦合到调理电路，并被配置为接收数据位并提供输出位。 输出电路还被配置为以多个操作模式之一操作，其中每个操作模式对应于不同的定时方案。 输出电路可以使用串联耦合的一对锁存器来实现。 可以通过例如选择性地将锁存器中的一个置于旁路模式来实现不同的操作模式。 定时电路可用于为输出电路提供必要的时钟信号。

    Memory integrated circuit with shared read/write line
    40.
    发明授权
    Memory integrated circuit with shared read/write line 失效
    具有共享读/写线的存储器集成电路

    公开(公告)号：US5963482A

    公开(公告)日：1999-10-05

    申请号：US115375

    申请日：1998-07-14

    申请人： Hua Zheng

    发明人： Hua Zheng

    IPC分类号： G11C7/10 ,  G11C11/4096 ,  G11C16/04

    CPC分类号： G11C7/106 ,  G11C11/4096 ,  G11C7/1051 ,  G11C7/1072

    摘要： A memory device is provided with N>1 memory arrays. Each of the memory arrays comprises a plurality of memory cells arranged into rows and columns. N I/O lines are provided that can be simultaneously activated during a prefetch cycle. Each of the I/O lines is connected to the memory cells of a different one of the N memory arrays for transferring data signals to and from specific addressed ones of the memory cells of the respective memory array. N latches are also provided wherein each of the latches is connected to a different one of the I/O lines. Furthermore, a read/write line is connected to each of the latches and extends along an edge of each memory array. During a prefetch cycle, each of the N I/O lines simultaneously transfers a data signal thereon. Each of the N latches receives a different phase clock signal for synchronizing a transfer of N data signals, including one data signal of each of the latches. The data signals are transferred between the latches and the read/write line so that each data signal is transferred during a respective different n.sup.th interval of a transfer cycle, where 1.ltoreq.n.ltoreq.N. As such, N data signals, including one data signal originating at, or destined to, each of the N memory arrays, are transferred sequentially via the read/write line during the prefetch cycle.

    摘要翻译： 存储器件具有N> 1个存储器阵列。 每个存储器阵列包括布置成行和列的多个存储器单元。 提供了可在预取周期期间同时激活的N I / O线。 每个I / O线连接到N个存储器阵列中不同的一个存储器阵列的存储器单元，用于将数据信号传送到相应存储器阵列的特定寻址存储器单元中的数据信号。 还提供了N个锁存器，其中每个锁存器连接到不同的I / O线路。 此外，读/写线连接到每个锁存器并且沿着每个存储器阵列的边缘延伸。 在预取周期期间，每个N I / O线同时在其上传送数据信号。 N个锁存器中的每一个接收不同的相位时钟信号，用于同步N个数据信号的传送，包括每个锁存器的一个数据信号。 数据信号在锁存器和读/写线之间传送，使得每个数据信号在传输周期的相应不同的第n个间隔期间被传送，其中1≤n≤N。 因此，在预取周期期间，N个数据信号，包括始发于或目的地为每个N个存储器阵列的一个数据信号经由读取/写入线顺序传送。