-
公开(公告)号：US20130321674A1
公开(公告)日：2013-12-05
申请号：US13484842
申请日：2012-05-31
摘要： Systems and methods for correcting geometric distortion are provided. In one example, an electronic device may include an imaging device, which may obtain image data of a first resolution, and geometric distortion and scaling logic. The imaging device may include a sensor and a lens that causes some geometric distortion in the image data. The geometric distortion correction and scaling logic may scale and correct for geometric distortion in the image data by determining first pixel coordinates in uncorrected or partially corrected image data that, when resampled, would produce corrected output image data at second pixel coordinates. The geometric distortion correction and scaling logic may resample pixels around the image data at the first pixel coordinates to obtain the corrected output image data at the second pixel coordinates. The corrected output image data may be of a second resolution.
摘要翻译： 提供了校正几何失真的系统和方法。 在一个示例中，电子设备可以包括可以获得第一分辨率的图像数据和几何失真和缩放逻辑的成像设备。 成像装置可以包括导致图像数据中的几何失真的传感器和透镜。 几何失真校正和缩放逻辑可以通过确定未校正或部分校正的图像数据中的第一像素坐标来缩放和校正图像数据中的几何失真，当被重新采样时，将在第二像素坐标处产生校正的输出图像数据。 几何失真校正和缩放逻辑可以在第一像素坐标处对图像数据周围的像素进行重新采样，以获得第二像素坐标处的经校正的输出图像数据。 经校正的输出图像数据可以是第二分辨率。
-
公开(公告)号：US20120131306A1
公开(公告)日：2012-05-24
申请号：US12950293
申请日：2010-11-19
申请人： Joseph P. Bratt , Peter F. Holland
发明人： Joseph P. Bratt , Peter F. Holland
IPC分类号： G06F12/10
CPC分类号： G06F12/0215 , G06F12/0802 , G06F12/0862 , G06F12/1027 , G06F12/123 , G06F2212/302 , G06F2212/654
摘要： In an embodiment, a display pipe includes one or more translation units corresponding to images that the display pipe is reading for display. Each translation unit may be configured to prefetch translations ahead of the image data fetches, which may prevent translation misses in the display pipe (at least in most cases). The translation units may maintain translations in first-in, first-out (FIFO) fashion, and the display pipe fetch hardware may inform the translation unit when a given translation or translation is no longer needed. The translation unit may invalidate the identified translations and prefetch additional translation for virtual pages that are contiguous with the most recently prefetched virtual page.
摘要翻译： 在一个实施例中，显示管道包括与显示管正在读取以供显示的图像对应的一个或多个平移单元。 每个翻译单元可以被配置为在图像数据提取之前预取翻译，这可以防止显示管道中的翻译缺失（至少在大多数情况下）。 翻译单元可以以先入先出（FIFO）方式保持翻译，并且显示管取出硬件可以在不再需要给定的翻译或翻译时通知翻译单元。 翻译单元可以使所识别的翻译失效，并且为与最近预取的虚拟页面连续的虚拟页面预取附加翻译。
-
33.发明申请IMAGE SIGNAL PROCESSOR LINE BUFFER CONFIGURATION FOR PROCESSING RAW IMAGE DATA 有权用于处理RAW图像数据的图像信号处理器线缓冲器配置公开(公告)号：US20120081578A1
公开(公告)日：2012-04-05
申请号：US12895396
申请日：2010-09-30
IPC分类号： H04N5/225
CPC分类号： H04N9/045 , G06T3/4015
摘要： The present disclosure provides techniques relates to the implementation of a raw pixel processing unit using a set of line buffers. In one embodiment, the set of line buffers may include a first subset and second subset. Various logical units of the raw pixel processing unit may be implemented using the first and second subsets of line buffers in a shared manner. For instance, in one embodiment, defective pixel correction and detection logic may be implemented using the first subset of line buffers. The second subset of line buffers may be used to implement lens shading correction logic, gain, offset, and clamping logic, and demosaicing logic. Further, noise reduction may also be implemented using at least a portion of each of the first and second subsets of line buffers.
摘要翻译： 本公开提供了技术涉及使用一组行缓冲器的原始像素处理单元的实现。 在一个实施例中，行缓冲器组可以包括第一子集和第二子集。 可以以共享的方式使用第一和第二子行的行缓冲器来实现原始像素处理单元的各种逻辑单元。 例如，在一个实施例中，可以使用线缓冲器的第一子集来实现有缺陷的像素校正和检测逻辑。 行缓冲器的第二子集可用于实现镜头阴影校正逻辑，增益，偏移和钳位逻辑以及去马赛克逻辑。 此外，还可以使用行缓冲器的第一和第二子集中的每一个的至少一部分来实现噪声降低。
-
公开(公告)号：US20110246806A1
公开(公告)日：2011-10-06
申请号：US13160234
申请日：2011-06-14
IPC分类号： G06F1/28
CPC分类号： G06F1/30 , G06F1/3203 , G06F1/3287 , Y02D10/171
摘要： A system and method is disclosed for efficiently managing power distribution among the various functional blocks used within portable electronic devices. The method includes allowing each functional block to be independently controlled, containing its own low-level software and power controls for setting the local power state of the functional block. For each power control domain in the implementation, hardware uses these local power states and determines and sets the actual operating state of the power control domain accordingly.
摘要翻译： 公开了一种用于在便携式电子设备中使用的各种功能块之间有效管理功率分配的系统和方法。 该方法包括允许每个功能块被独立控制，包含其自己的低级软件和用于设置功能块的本地功率状态的功率控制。 对于实施中的每个功率控制域，硬件使用这些本地电源状态，并相应地确定和设置功率控制域的实际工作状态。
-
35.发明授权公开(公告)号：US07808503B2
公开(公告)日：2010-10-05
申请号：US11613093
申请日：2006-12-19
申请人： Jerome F. Duluk, Jr. , Richard E. Hessel , Vaughn T. Arnold , Jack Benkual , Joseph P. Bratt , George Cuan , Stephen L. Dodgen , Emerson S. Fang , Zhaoyu Gong , Thomas Y. Yo , Hengwei Hsu , Sidong Li , Sam Ng , Matthew N. Papakipos , Jason R. Redgrave , Sushma S. Trivedi , Nathan D. Tuck , Shun Wai Go , Lindy Fung , Tuan D. Nguyen , Joseph P. Grass , Bo Hong , Abraham Mammen , Abbas Rashid , Albert Suan-Wei Tsay
发明人： Jerome F. Duluk, Jr. , Richard E. Hessel , Vaughn T. Arnold , Jack Benkual , Joseph P. Bratt , George Cuan , Stephen L. Dodgen , Emerson S. Fang , Zhaoyu Gong , Thomas Y. Yo , Hengwei Hsu , Sidong Li , Sam Ng , Matthew N. Papakipos , Jason R. Redgrave , Sushma S. Trivedi , Nathan D. Tuck , Shun Wai Go , Lindy Fung , Tuan D. Nguyen , Joseph P. Grass , Bo Hong , Abraham Mammen , Abbas Rashid , Albert Suan-Wei Tsay
CPC分类号： G06T15/20 , G06T1/60 , G06T11/001 , G06T11/40 , G06T15/005 , G06T15/04 , G06T15/30 , G06T15/40 , G06T15/50 , G06T15/80 , G06T15/83 , G06T15/87
摘要： A deferred shading graphics pipeline processor and method are provided encompassing numerous substructures. Embodiments of the processor and method may include one or more of deferred shading, a tiled frame buffer, and multiple?stage hidden surface removal processing. In the deferred shading graphics pipeline, hidden surface removal is completed before pixel coloring is done. The pipeline processor comprises a command fetch and decode unit, a geometry unit, a mode extraction unit, a sort unit, a setup unit, a cull unit, a mode injection unit, a fragment unit, a texture unit, a Phong lighting unit, a pixel unit, and a backend unit.
摘要翻译： 提供了包括许多子结构的延迟着色图形流水线处理器和方法。 处理器和方法的实施例可以包括延迟着色，平铺帧缓冲器和多级隐藏表面去除处理中的一个或多个。 在延迟阴影图形管道中，在完成像素着色之前完成隐藏表面移除。 流水线处理器包括命令提取和解码单元，几何单元，模式提取单元，分类单元，设置单元，剔除单元，模式注入单元，片段单元，纹理单元，Phong照明单元， 像素单元和后端单元。
-
36.发明授权Method for variable length decoding using multiple configurable look-up tables 有权使用多个可配置查找表进行可变长度解码的方法公开(公告)号：US07681013B1
公开(公告)日：2010-03-16
申请号：US10038473
申请日：2001-12-31
IPC分类号： G06F9/30
CPC分类号： G06F9/30032 , G06F9/30014 , G06F9/30047 , G06F9/30101 , G06F9/30109 , G06F9/3013 , G06F9/30141 , G06F9/3802 , G06F9/3836 , G06F9/3853 , G06F9/3877 , G06F9/3879 , G06F9/3885 , G06F9/3895
摘要： Methods and apparatuses for variable length decoding using multiple look-up tables simultaneously. In one aspect of the invention, a method for execution by a microprocessor in response to receiving a single instruction includes: receiving a string of bits; generating a plurality of indices using a plurality of segments of bits in the string of bits; looking up simultaneously a plurality of entries from a plurality of look-up tables using the plurality of indices; and combining the plurality of entries into a first result. The above operations are performed in response to the microprocessor receiving the single instruction.
摘要翻译： 同时使用多个查找表进行可变长度解码的方法和装置。 在本发明的一个方面，微处理器响应于接收单个指令而执行的方法包括：接收一串比特; 使用所述比特串中的多个比特段来生成多个索引; 使用多个索引从多个查找表中同时查找多个条目; 以及将所述多个条目组合成第一结果。 响应于微处理器接收到单个指令执行上述操作。
-
公开(公告)号：US07305540B1
公开(公告)日：2007-12-04
申请号：US10038742
申请日：2001-12-31
申请人： Sushma Shrikant Trivedi , Joseph P. Bratt , Jack Benkual , Vaughn Todd Arnold , Derek Fujio Iwamoto
发明人： Sushma Shrikant Trivedi , Joseph P. Bratt , Jack Benkual , Vaughn Todd Arnold , Derek Fujio Iwamoto
CPC分类号： G06F9/3885 , G06F9/30014 , G06F9/30032 , G06F9/30036 , G06F9/3004 , G06F9/30047 , G06F9/30101 , G06F9/3802 , G06F9/382 , G06F9/3853 , G06F9/3879 , G06F15/8053
摘要： Methods and apparatuses for a data processing system are described herein. In one aspect of the invention, an exemplary apparatus includes a chip interconnect, a memory controller for controlling the host memory comprising DRAM memory, the memory controller coupled to the chip interconnect, a scalar processing unit coupled the chip interconnect wherein the scalar processing unit is capable of executing instructions to perform scalar data processing, a vector processing unit coupled the chip interconnect wherein the vector processing unit is capable of executing instructions to perform vector data processing, and an input/output (I/O) interface coupled to the chip interconnect wherein the I/O interface receives/transmits data from/to the scalar and/or vector processing units.
摘要翻译： 本文描述了用于数据处理系统的方法和装置。 在本发明的一个方面中，示例性装置包括芯片互连，用于控制主机存储器的存储器控制器，其包括DRAM存储器，耦合到芯片互连的存储器控制器，耦合芯片互连的标量处理单元，其中标量处理单元 能够执行指令执行标量数据处理的矢量处理单元，耦合芯片互连的矢量处理单元，其中矢量处理单元能够执行执行向量数据处理的指令，以及耦合到芯片互连的输入/输出（I / O） 其中I / O接口从标量和/或向量处理单元接收/发送数据。
-
公开(公告)号：US07015921B1
公开(公告)日：2006-03-21
申请号：US10038905
申请日：2001-12-31
IPC分类号： G09G5/36
CPC分类号： G06F12/0831 , G06F13/1668
摘要： An apparatus, in a data processing system having at least one host processor with host processor cache and host memory, includes a chip interconnect, a cache coherent interface coupled to the chip interconnect wherein the cache coherent interface provides cache coherent access, a cache non-coherent interface coupled to the chip interconnect wherein the cache non-coherent interface provides cache non-coherent access to the host memory, and a compute engine coupled to the chip interconnect and coupled to the cache coherent interface and coupled to cache non-coherent interface wherein the compute engine issues a memory access request. Other methods and apparatuses are also described.
摘要翻译： 具有至少一个具有主处理器高速缓存和主机存储器的主机处理器的数据处理系统中的装置包括芯片互连，耦合到芯片互连的高速缓存相干接口，其中高速缓存相干接口提供高速缓存一致性访问， 耦合到芯片互连的相干接口，其中高速缓存非相干接口提供对主机存储器的高速缓存非相干访问，以及耦合到芯片互连并耦合到高速缓存相干接口并耦合到高速缓存非相干接口的计算引擎，其中 计算引擎发出内存访问请求。 还描述了其它方法和装置。
-
39.发明授权公开(公告)号：US06717576B1
公开(公告)日：2004-04-06
申请号：US09377503
申请日：1999-08-20
申请人： Jerome F. Duluk, Jr. , Richard E. Hessel , Vaughn T. Arnold , Jack Benkual , Joseph P. Bratt , George Cuan , Stephen L. Dodgen , Emerson S. Fang , Zhaoyu Gong , Thomas Y. Ho , Hengwei Hsu , Sidong Li , Sam Ng , Matthew N. Papakipos , Jason R. Redgrave , Sushma S. Trivedi , Nathan D. Tuck , Shun Wai Go , Lindy Fung , Tuan D. Nguyen , Joseph P. Grass , Bo Hong , Abraham Mammen , Abbas Rashid , Albert Suan-Wei Tsay
发明人： Jerome F. Duluk, Jr. , Richard E. Hessel , Vaughn T. Arnold , Jack Benkual , Joseph P. Bratt , George Cuan , Stephen L. Dodgen , Emerson S. Fang , Zhaoyu Gong , Thomas Y. Ho , Hengwei Hsu , Sidong Li , Sam Ng , Matthew N. Papakipos , Jason R. Redgrave , Sushma S. Trivedi , Nathan D. Tuck , Shun Wai Go , Lindy Fung , Tuan D. Nguyen , Joseph P. Grass , Bo Hong , Abraham Mammen , Abbas Rashid , Albert Suan-Wei Tsay
IPC分类号： G06T1500
CPC分类号： G06T15/30 , G06T11/40 , G06T15/005 , G06T15/04 , G06T15/20 , G06T15/405 , G06T15/50 , G06T15/83
摘要： A deferred shading graphics pipeline processor and method are provided encompassing numerous substructures. Embodiments of the processor and method may include one or more of deferred shading, a tiled frame buffer, and multiple-stage hidden surface removal processing. In the deferred shading graphics pipeline, hidden surface removal is completed before pixel coloring is done. The pipeline processor comprises a command fetch and decode unit, a geometry unit, a mode extraction unit, a sort unit, a setup unit, a cull unit, a mode injection unit, a fragment unit, a texture unit, a Phong lighting unit, a pixel unit, and a backend unit.
摘要翻译： 提供了包括许多子结构的延迟着色图形流水线处理器和方法。 处理器和方法的实施例可以包括延迟着色，平铺帧缓冲器和多级隐藏表面去除处理中的一个或多个。 在延迟阴影图形管道中，在完成像素着色之前完成隐藏表面移除。 流水线处理器包括命令提取和解码单元，几何单元，模式提取单元，分类单元，设置单元，剔除单元，模式注入单元，片段单元，纹理单元，Phong照明单元， 像素单元和后端单元。
-
公开(公告)号：US08917336B2
公开(公告)日：2014-12-23
申请号：US13484842
申请日：2012-05-31
IPC分类号： H04N5/217
摘要： Systems and methods for correcting geometric distortion are provided. In one example, an electronic device may include an imaging device, which may obtain image data of a first resolution, and geometric distortion and scaling logic. The imaging device may include a sensor and a lens that causes some geometric distortion in the image data. The geometric distortion correction and scaling logic may scale and correct for geometric distortion in the image data by determining first pixel coordinates in uncorrected or partially corrected image data that, when resampled, would produce corrected output image data at second pixel coordinates. The geometric distortion correction and scaling logic may resample pixels around the image data at the first pixel coordinates to obtain the corrected output image data at the second pixel coordinates. The corrected output image data may be of a second resolution.
摘要翻译： 提供了校正几何失真的系统和方法。 在一个示例中，电子设备可以包括可以获得第一分辨率的图像数据和几何失真和缩放逻辑的成像设备。 成像装置可以包括导致图像数据中的几何失真的传感器和透镜。 几何失真校正和缩放逻辑可以通过确定未校正或部分校正的图像数据中的第一像素坐标来缩放和校正图像数据中的几何失真，当被重新采样时，将在第二像素坐标处产生校正的输出图像数据。 几何失真校正和缩放逻辑可以在第一像素坐标处对图像数据周围的像素进行重新采样，以获得第二像素坐标处的经校正的输出图像数据。 经校正的输出图像数据可以是第二分辨率。
-
-
-
-
-
-
-
-
-
搜索结果
74 条记录 (耗时 0.104 秒)