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1067 条记录 (耗时 0.036 秒)

    Methods of forming graphene-containing switches
    31.
    发明授权
    Methods of forming graphene-containing switches 有权

    公开(公告)号：US08394682B2

    公开(公告)日：2013-03-12

    申请号：US13191192

    申请日：2011-07-26

    申请人： Gurtej S. Sandhu

    发明人： Gurtej S. Sandhu

    IPC分类号： H01L21/82

    CPC分类号： H01L21/768 ,  H01L23/525 ,  H01L23/53276 ,  H01L29/0665 ,  H01L29/0676 ,  H01L29/1606 ,  H01L29/66022 ,  H01L29/66742 ,  H01L29/7788 ,  H01L29/78642 ,  H01L29/78684 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Some embodiments include methods of forming graphene-containing switches. A bottom electrode may be formed over a base, and a first electrically conductive structure may be formed to extend upwardly from the bottom electrode. Dielectric material may be formed along a sidewall of the first electrically conductive structure, while leaving a portion of the bottom electrode exposed. A graphene structure may be formed to be electrically coupled with the exposed portion of the bottom electrode. A second electrically conductive structure may be formed on an opposing side of the graphene structure from the first electrically conductive structure. A top electrode may be formed over the graphene structure and electrically coupled with the second electrically conductive structure. The first and second electrically conductive structures may be configured to provide an electric field across the graphene structure.

    Nanotube separation methods
    32.
    发明授权
    Nanotube separation methods 有权

    公开(公告)号：US08361328B2

    公开(公告)日：2013-01-29

    申请号：US13276150

    申请日：2011-10-18

    申请人： Gurtej S. Sandhu

    发明人： Gurtej S. Sandhu

    IPC分类号： C02F1/68

    CPC分类号： B01D21/262 ,  B01D43/00 ,  B82Y30/00 ,  B82Y40/00 ,  C01B32/172 ,  Y10S977/745 ,  Y10S977/746 ,  Y10S977/845 ,  Y10S977/847

    摘要： A nanotube separation method includes depositing a tag on a nanotube in a nanotube mixture. The nanotube has a defect and the tag deposits at the defect where a deposition rate is greater than on another nanotube in the mixture lacking the defect. The method includes removing the tagged nanotube from the mixture by using the tag. As one option, the tag may contain a ferromagnetic material and the removing may include applying a magnetic field. As another option, the tag may contain an ionic material and the removing may include applying an electric field. As a further option, the tag may contain an atom having an atomic mass greater than the atomic mass of carbon and the removing may include applying a centrifugal force to the nanotube mixture. Any two or more of the indicated removal techniques may be combined.

    Spin torque transfer memory cell structures and methods
    33.
    发明授权
    Spin torque transfer memory cell structures and methods 有权
    旋转转矩记忆单元结构和方法

    公开(公告)号：US08358534B2

    公开(公告)日：2013-01-22

    申请号：US12885012

    申请日：2010-09-17

    申请人： Stephen J. Kramer ,  Gurtej S. Sandhu

    发明人： Stephen J. Kramer ,  Gurtej S. Sandhu

    IPC分类号： G11C11/15

    CPC分类号： H01L43/02 ,  G11C11/161 ,  G11C11/1675 ,  H01L27/228 ,  H01L43/08

    摘要： Spin Torque Transfer (STT) memory cell structures and methods are described herein. One or more STT memory cell structures include a tunneling barrier material positioned between a ferromagnetic storage material and a pinned ferromagnetic material in contact with an antiferromagnetic material and a multiferroic material in contact with the ferromagnetic storage material, wherein the antiferromagnetic material, the ferromagnetic storage material, and the pinned ferromagnetic material are located between a first electrode and a second electrode.

    摘要翻译： 本文描述了旋转转矩传递（STT）存储单元结构和方法。 一个或多个STT存储器单元结构包括位于铁磁存储材料和与反铁磁材料接触的被钉扎铁磁材料和与铁磁存储材料接触的多铁性材料之间的隧道势垒材料，其中反铁磁材料铁磁存储材料 并且被钉扎的铁磁材料位于第一电极和第二电极之间。

    Methods of Fabricating Substrates
    34.
    发明申请
    Methods of Fabricating Substrates 有权
    制造基板的方法

    公开(公告)号：US20120322269A1

    公开(公告)日：2012-12-20

    申请号：US13596430

    申请日：2012-08-28

    申请人： Scott Sills ,  Gurtej S. Sandhu ,  Anton deVilliers

    发明人： Scott Sills ,  Gurtej S. Sandhu ,  Anton deVilliers

    IPC分类号： H01L21/311

    CPC分类号： H01L21/31138 ,  H01L21/0273 ,  H01L21/0337 ,  H01L21/0338

    摘要： A method of fabricating a substrate includes forming first and second spaced features over a substrate. The first spaced features have elevationally outermost regions which are different in composition from elevationally outermost regions of the second spaced features. The first and second spaced features alternate with one another. Every other first feature is removed from the substrate and pairs of immediately adjacent second features are formed which alternate with individual of remaining of the first features. After such act of removing, the substrate is processed through a mask pattern comprising the pairs of immediately adjacent second features which alternate with individual of the remaining of the first features. Other embodiments are disclosed.

    摘要翻译： 一种制造衬底的方法包括在衬底上形成第一和第二间隔的特征。 第一间隔的特征具有与第二间隔特征的垂直最外区域不同的高度最外的区域。 第一和第二间隔的特征彼此交替。 每个其他第一特征从衬底移除，并且形成直接相邻的第二特征对，其与第一特征的剩余部分的个体交替。 在这样的去除动作之后，通过掩模图案来处理衬底，该掩模图案包括与第一特征剩余部分的个体交替的紧邻的第二特征对。 公开了其他实施例。

    Method and structure for integrating capacitor-less memory cell with logic
    37.
    发明授权
    Method and structure for integrating capacitor-less memory cell with logic 有权
    将无电容器存储单元与逻辑集成的方法和结构

    公开(公告)号：US08278167B2

    公开(公告)日：2012-10-02

    申请号：US12338404

    申请日：2008-12-18

    申请人： Gurtej S. Sandhu

    发明人： Gurtej S. Sandhu

    IPC分类号： H01L21/8238

    CPC分类号： H01L27/10844 ,  H01L21/84 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/10802 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/1203

    摘要： Methods for fabricating integrated circuits include fabricating a logic device on a substrate, forming an intermediate semiconductor substrate on a surface of the logic device, and fabricating a capacitor-less memory cell on the intermediate semiconductor substrate. Integrated circuits with capacitor-less memory cells formed on a surface of a logic device are also disclosed, as are multi-core microprocessors including such integrated circuits.

    摘要翻译： 制造集成电路的方法包括在衬底上制造逻辑器件，在逻辑器件的表面上形成中间半导体衬底，以及在中间半导体衬底上制造无电容器的存储单元。 还公开了在逻辑器件的表面上形成有无电容器的存储器单元的集成电路，以及包括这种集成电路的多核微处理器。

    Methods of fabricating substrates
    38.
    发明授权
    Methods of fabricating substrates 有权
    制造基板的方法

    公开(公告)号：US08273634B2

    公开(公告)日：2012-09-25

    申请号：US12328435

    申请日：2008-12-04

    申请人： Scott Sills ,  Gurtej S. Sandhu ,  Anton deVilliers

    发明人： Scott Sills ,  Gurtej S. Sandhu ,  Anton deVilliers

    IPC分类号： H01L21/331 ,  H01L21/8222

    CPC分类号： H01L21/31138 ,  H01L21/0273 ,  H01L21/0337 ,  H01L21/0338

    摘要： A method of fabricating a substrate includes forming first and second spaced features over a substrate. The first spaced features have elevationally outermost regions which are different in composition from elevationally outermost regions of the second spaced features. The first and second spaced features alternate with one another. Every other first feature is removed from the substrate and pairs of immediately adjacent second features are formed which alternate with individual of remaining of the first features. After such act of removing, the substrate is processed through a mask pattern comprising the pairs of immediately adjacent second features which alternate with individual of the remaining of the first features. Other embodiments are disclosed.

    摘要翻译： 一种制造衬底的方法包括在衬底上形成第一和第二间隔的特征。 第一间隔的特征具有与第二间隔特征的垂直最外区域不同的高度最外的区域。 第一和第二间隔的特征彼此交替。 每个其他第一特征从衬底移除，并且形成直接相邻的第二特征对，其与第一特征的剩余部分的个体交替。 在这样的去除动作之后，通过掩模图案来处理衬底，该掩模图案包括与第一特征剩余部分的个体交替的紧邻的第二特征对。 公开了其他实施例。

    Methods of Forming High Density Structures and Low Density Structures with a Single Photomask
    39.
    发明申请
    Methods of Forming High Density Structures and Low Density Structures with a Single Photomask 有权
    用单一光掩模形成高密度结构和低密度结构的方法

    公开(公告)号：US20120238077A1

    公开(公告)日：2012-09-20

    申请号：US13485869

    申请日：2012-05-31

    申请人： Ramakanth Alapati ,  Ardavan Niroomand ,  Gurtej S. Sandhu

    发明人： Ramakanth Alapati ,  Ardavan Niroomand ,  Gurtej S. Sandhu

    IPC分类号： H01L21/302 ,  H01L21/20

    CPC分类号： H01L21/32139 ,  H01L21/0337 ,  H01L21/31144 ,  H01L27/11526 ,  H01L27/11543

    摘要： Some embodiments include formation of polymer spacers along sacrificial material, removal of the sacrificial material, and utilization of the polymer spacers as masks during fabrication of integrated circuitry. The polymer spacer masks may, for example, be utilized to pattern flash gates of a flash memory array. In some embodiments, the polymer is simultaneously formed across large sacrificial structures and small sacrificial structures. The polymer is thicker across the large sacrificial structures than across the small sacrificial structures, and such difference in thickness is utilized to fabricate high density structures and low-density structures with a single photomask.

    摘要翻译： 一些实施方案包括沿着牺牲材料形成聚合物间隔物，去除牺牲材料，以及在制造集成电路期间利用聚合物间隔物作为掩模。 聚合物间隔物掩模可以例如用于对闪存阵列的闪光栅图案进行图案化。 在一些实施方案中，聚合物同时形成跨越大的牺牲结构和小的牺牲结构。 聚合物在大的牺牲结构上比通过小的牺牲结构更厚，并且这种厚度的差异被用于利用单个光掩模制造高密度结构和低密度结构。

    Methods of fabricating substrates
    40.
    发明授权
    Methods of fabricating substrates 有权
    制造基板的方法

    公开(公告)号：US08247302B2

    公开(公告)日：2012-08-21

    申请号：US12328464

    申请日：2008-12-04

    申请人： Scott Sills ,  Gurtej S. Sandhu ,  Anton deVilliers

    发明人： Scott Sills ,  Gurtej S. Sandhu ,  Anton deVilliers

    IPC分类号： H01L21/331 ,  H01L21/8222

    CPC分类号： H01L21/31138 ,  G03F7/0035 ,  H01L21/0273 ,  H01L21/0337 ,  H01L21/0338

    摘要： A method of fabricating a substrate includes forming spaced first features and spaced second features over a substrate. The first and second features alternate with one another and are spaced relative one another. Width of the spaced second features is laterally trimmed to a greater degree than any lateral trimming of width of the spaced first features while laterally trimming width of the spaced second features. After laterally trimming of the second features, spacers are formed on sidewalls of the spaced first features and on sidewalls of the spaced second features. The spacers are of some different composition from that of the spaced first features and from that of the spaced second features. After forming the spacers, the spaced first features and the spaced second features are removed from the substrate. The substrate is processed through a mask pattern comprising the spacers. Other embodiments are disclosed.

    摘要翻译： 一种制造衬底的方法包括在衬底上形成间隔开的第一特征和间隔开的第二特征。 第一和第二特征彼此交替并彼此间隔开。 间隔开的第二特征的宽度被横向修剪到比间隔开的第一特征的宽度的任何横向修剪更大的程度，同时横向修剪间隔开的第二特征的宽度。 在第二特征的横向修剪之后，间隔物形成在间隔开的第一特征的侧壁上并且在间隔开的第二特征的侧壁上。 间隔物与间隔开的第一特征和间隔开的第二特征的间隔物具有不同的组成。 在形成间隔物之后，从衬底移除间隔开的第一特征和间隔开的第二特征。 通过包括间隔物的掩模图案处理衬底。 公开了其他实施例。