公开(公告)号：US08673699B2

公开(公告)日：2014-03-18

申请号：US13551054

申请日：2012-07-17

申请人： Thomas N. Adam ,  Kangguo Cheng ,  Bruce B. Doris ,  Bala S. Haran ,  Pranita Kulkarni ,  Amlan Majumdar ,  Stefan Schmitz

发明人： Thomas N. Adam ,  Kangguo Cheng ,  Bruce B. Doris ,  Bala S. Haran ,  Pranita Kulkarni ,  Amlan Majumdar ,  Stefan Schmitz

IPC分类号： H01L21/00

CPC分类号： H01L21/84 ,  H01L27/1203

摘要： A method of forming a semiconductor structure which includes an extremely thin silicon-on-insulator (ETSOI) semiconductor structure having a PFET portion and an NFET portion, a gate structure in the PFET portion and the NFET portion, a high quality nitride spacer adjacent to the gate structures in the PFET portion and the NFET portion and a doped faceted epitaxial silicon germanium raised source/drain (RSD) in the PFET portion. An amorphous silicon layer is formed on the RSD in the PFET portion. A faceted epitaxial silicon RSD is formed on the ETSOI adjacent to the high quality nitride in the NFET portion. The amorphous layer in the PFET portion prevents epitaxial growth in the PFET portion during formation of the RSD in the NFET portion. Extensions are ion implanted into the ETSOI underneath the gate structure in the NFET portion.

摘要翻译： 一种形成半导体结构的方法，其包括具有PFET部分和NFET部分的极薄的绝缘体上硅（ETSOI）半导体结构，PFET部分中的栅极结构和NFET部分，邻近 PFET部分中的栅极结构和NFET部分以及PFET部分中的掺杂多面外延硅锗升高源极/漏极（RSD）。 在PFET部分的RSD上形成非晶硅层。 在与NFET部分中的高质量氮化物相邻的ETSOI上形成刻面外延硅RSD。 PFET部分中的非晶层防止在NFET部分中形成RSD期间在PFET部分中的外延生长。 扩展件被离子注入到NFET部分中的栅极结构下面的ETSOI中。

公开(公告)号：US20140024181A1

公开(公告)日：2014-01-23

申请号：US13551054

申请日：2012-07-17

申请人： Thomas N. Adam ,  Kangguo Cheng ,  Bruce B. Doris ,  Bala S. Haran ,  Pranita Kulkarni ,  Amlan Majumdar ,  Stefan Schmitz

发明人： Thomas N. Adam ,  Kangguo Cheng ,  Bruce B. Doris ,  Bala S. Haran ,  Pranita Kulkarni ,  Amlan Majumdar ,  Stefan Schmitz

IPC分类号： H01L21/8238

CPC分类号： H01L21/84 ,  H01L27/1203

摘要： A method of forming a semiconductor structure which includes an extremely thin silicon-on-insulator (ETSOI) semiconductor structure having a PFET portion and an NFET portion, a gate structure in the PFET portion and the NFET portion, a high quality nitride spacer adjacent to the gate structures in the PFET portion and the NFET portion and a doped faceted epitaxial silicon germanium raised source/drain (RSD) in the PFET portion. An amorphous silicon layer is formed on the RSD in the PFET portion. A faceted epitaxial silicon RSD is formed on the ETSOI adjacent to the high quality nitride in the NFET portion. The amorphous layer in the PFET portion prevents epitaxial growth in the PFET portion during formation of the RSD in the NFET portion. Extensions are ion implanted into the ETSOI underneath the gate structure in the NFET portion.

摘要翻译： 一种形成半导体结构的方法，其包括具有PFET部分和NFET部分的极薄的绝缘体上硅（ETSOI）半导体结构，PFET部分中的栅极结构和NFET部分，高质量氮化物间隔物 PFET部分中的栅极结构和NFET部分以及PFET部分中的掺杂多面外延硅锗升高源极/漏极（RSD）。 在PFET部分的RSD上形成非晶硅层。 在与NFET部分中的高质量氮化物相邻的ETSOI上形成刻面外延硅RSD。 PFET部分中的非晶层防止在NFET部分中形成RSD期间在PFET部分中的外延生长。 扩展件被离子注入到NFET部分中的栅极结构下面的ETSOI中。

公开(公告)号：US08546203B1

公开(公告)日：2013-10-01

申请号：US13551100

申请日：2012-07-17

申请人： Kangguo Cheng ,  Bruce B. Doris ,  Bala S. Haran ,  Pranita Kulkarni ,  Nicolas Loubet ,  Amlan Majumdar ,  Stefan Schmitz

发明人： Kangguo Cheng ,  Bruce B. Doris ,  Bala S. Haran ,  Pranita Kulkarni ,  Nicolas Loubet ,  Amlan Majumdar ,  Stefan Schmitz

IPC分类号： H01L21/00

CPC分类号： H01L21/84 ,  H01L29/66628

摘要： Method of forming a semiconductor structure which includes an extremely thin silicon-on-insulator (ETSOI) semiconductor structure having a PFET portion and an NFET portion, a gate structure in the PFET portion and the NFET portion, a high quality nitride spacer adjacent to the gate structures in the PFET portion and the NFET portion and a doped faceted epitaxial silicon germanium raised source/drain (RSD) in the PFET portion. Low quality nitride and high quality nitride are formed on the semiconductor structure. The high quality nitride in the NFET portion is damaged by ion implantation to facilitate its removal. A faceted epitaxial silicon RSD is formed on the ETSOI adjacent to the high quality nitride in the NFET portion. The high quality nitride in the PFET portion is damaged by ion implantation to facilitate its removal. Extensions are ion implanted into the ETSOI underneath the gate structure in the NFET portion.

摘要翻译： 形成半导体结构的方法包括具有PFET部分和NFET部分的极薄的绝缘上硅（ETSOI）半导体结构，PFET部分中的栅极结构和NFET部分，与 PFET部分中的栅极结构和NFET部分以及PFET部分中的掺杂多面外延硅锗升高源极/漏极（RSD）。 在半导体结构上形成低质量的氮化物和高质量的氮化物。 NFET部分中的高质量氮化物被离子注入损坏以便于其去除。 在与NFET部分中的高质量氮化物相邻的ETSOI上形成刻面外延硅RSD。 PFET部分中的高质量氮化物被离子注入损坏以便于其去除。 扩展件被离子注入到NFET部分中的栅极结构下面的ETSOI中。

公开(公告)号：US08372705B2

公开(公告)日：2013-02-12

申请号：US13013801

申请日：2011-01-25

申请人： Lahir Shaik Adam ,  Sanjay C Mehta ,  Balasubramanian S Haran ,  Bruce B. Doris

发明人： Lahir Shaik Adam ,  Sanjay C Mehta ,  Balasubramanian S Haran ,  Bruce B. Doris

IPC分类号： H01L21/8238

CPC分类号： H01L29/78 ,  H01L21/823807 ,  H01L21/823864 ,  H01L27/092 ,  H01L29/4983 ,  H01L29/7843

摘要： CMOS transistors are formed incorporating a gate electrode having tensely stressed spacers on the gate sidewalls of an n channel field effect transistor and having compressively stressed spacers on the gate sidewalls of a p channel field effect transistor to provide differentially stressed channels in respective transistors to increase carrier mobility in the respective channels.

摘要翻译： 形成CMOS晶体管，其结合有在n沟道场效应晶体管的栅极侧壁上具有紧张应力间隔物的栅极，并且在ap沟道场效应晶体管的栅极侧壁上具有压缩应力间隔物，以在相应晶体管中提供差分应力通道以增加载流子迁移率 在各自的频道。

公开(公告)号：US20120187482A1

公开(公告)日：2012-07-26

申请号：US13013801

申请日：2011-01-25

申请人： Lahir S. Adam ,  Sanjay C. Mehta ,  Balasubramanian S. Haran ,  Bruce B. Doris

发明人： Lahir S. Adam ,  Sanjay C. Mehta ,  Balasubramanian S. Haran ,  Bruce B. Doris

IPC分类号： H01L21/8238 ,  H01L29/78

CPC分类号： H01L29/78 ,  H01L21/823807 ,  H01L21/823864 ,  H01L27/092 ,  H01L29/4983 ,  H01L29/7843

摘要： CMOS transistors are formed incorporating a gate electrode having tensely stressed spacers on the gate sidewalls of an n channel field effect transistor and having compressively stressed spacers on the gate sidewalls of a p channel field effect transistor to provide differentially stressed channels in respective transistors to increase carrier mobility in the respective channels.

摘要翻译： 形成CMOS晶体管，其结合有在n沟道场效应晶体管的栅极侧壁上具有紧张应力间隔物的栅极，并且在ap沟道场效应晶体管的栅极侧壁上具有压缩应力间隔物，以在相应晶体管中提供差分应力通道以增加载流子迁移率 在各自的频道。

公开(公告)号：US20110031503A1

公开(公告)日：2011-02-10

申请号：US12538627

申请日：2009-08-10

申请人： Bruce B. Doris ,  Johnathan E. Faltermeier ,  Lahir S. Adam ,  Balasubramanian S. Haran

发明人： Bruce B. Doris ,  Johnathan E. Faltermeier ,  Lahir S. Adam ,  Balasubramanian S. Haran

IPC分类号： H01L29/161 ,  H01L27/092 ,  H01L21/04 ,  H01L21/8238

CPC分类号： H01L21/823807 ,  H01L21/823814 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

摘要： An FET device is disclosed which contains a source and a drain that are each provided with an extension. The source and the drain, and their extensions, are composed of epitaxial materials containing Ge or C. The epitaxial materials and the Si substrate have differing lattice constants, consequently the source and the drain and their extensions are imparting a state of stress onto the channel. For a PFET device the epitaxial material may be SiGe, or Ge, and the channel may be in a compressive state of stress. For an NFET device the epitaxial material may be SiC and the channel may be in a tensile state of stress. A method for fabricating an FET device is also disclosed. One may form a first recession in the Si substrate to a first depth on opposing sides of the gate. The first recession is filled epitaxially with a first epitaxial material. Then, a second recession may be formed in the Si substrate to a second depth, which is greater than the first depth. Next, one may fill the second recession with a second epitaxial material, which is the same kind of material as the first epitaxial material. The epitaxial materials are selected to have a different lattice constant than the Si substrate, and consequently a state of stress is being imparted onto the channel.

摘要翻译： 公开了一种FET器件，其包含各自具有延伸部的源极和漏极。 源极和漏极及其延伸部分由包含Ge或C的外延材料组成。外延材料和Si衬底具有不同的晶格常数，因此源极和漏极及其延伸部分在沟道上赋予应力状态 。 对于PFET器件，外延材料可以是SiGe或Ge，并且沟道可以处于压应力的压缩状态。 对于NFET器件，外延材料可以是SiC，并且沟道可以处于应力的拉伸状态。 还公开了一种用于制造FET器件的方法。 可以在Si衬底中形成第一凹陷到栅极的相对侧上的第一深度。 用第一外延材料外延地填充第一次衰退。 然后，可以在Si衬底中形成比第一深度更大的第二深度的第二凹陷。 接下来，可以用与第一外延材料相同的材料的第二外延材料填充第二凹陷。 选择外延材料具有与Si衬底不同的晶格常数，并且因此在沟道上施加应力状态。

公开(公告)号：US08535999B2

公开(公告)日：2013-09-17

申请号：US12902624

申请日：2010-10-12

申请人： Lahir Adam ,  Bruce B. Doris ,  Sanjay Mehta ,  Zhengmao Zhu

发明人： Lahir Adam ,  Bruce B. Doris ,  Sanjay Mehta ,  Zhengmao Zhu

IPC分类号： H01L21/02

CPC分类号： H01L29/7847

摘要： Semiconductor substrate with a deformed gate region and a method for the fabrication thereof. The semiconductor substrate has improved device performance compared to devices without a deformed gate region and decreased dopant loss compared to devices with deformed source/drain regions.

摘要翻译： 具有变形栅极区域的半导体衬底及其制造方法。 与具有变形的源极/漏极区域的器件相比，半导体衬底与不具有变形栅极区域的器件相比具有改进的器件性能和降低的掺杂剂损耗。

公开(公告)号：US20120086071A1

公开(公告)日：2012-04-12

申请号：US12902624

申请日：2010-10-12

申请人： Lahir Shaik Adam ,  Bruce B. Doris ,  Sanjay Mehta ,  Zhengmao Zhu

发明人： Lahir Shaik Adam ,  Bruce B. Doris ,  Sanjay Mehta ,  Zhengmao Zhu

IPC分类号： H01L29/772 ,  H01L21/336

CPC分类号： H01L29/7847

摘要： Semiconductor substrate with a deformed gate region and a method for the fabrication thereof. The semiconductor substrate has improved device performance compared to devices without a deformed gate region and decreased dopant loss compared to devices with deformed source/drain regions.

摘要翻译： 具有变形栅极区域的半导体衬底及其制造方法。 与具有变形的源极/漏极区域的器件相比，半导体衬底与不具有变形栅极区域的器件相比具有改进的器件性能和降低的掺杂剂损耗。

公开(公告)号：US09041116B2

公开(公告)日：2015-05-26

申请号：US13478154

申请日：2012-05-23

申请人： Bruce B. Doris ,  Kangguo Cheng ,  Steven J. Holmes ,  Ali Khakifirooz ,  Pranita Kulkarni ,  Shom Ponoth ,  Raghavasimhan Sreenivasan ,  Stefan Schmitz

发明人： Bruce B. Doris ,  Kangguo Cheng ,  Steven J. Holmes ,  Ali Khakifirooz ,  Pranita Kulkarni ,  Shom Ponoth ,  Raghavasimhan Sreenivasan ,  Stefan Schmitz

IPC分类号： H01L27/092 ,  H01L27/12 ,  H01L21/8238

CPC分类号： H01L21/823835 ,  H01L21/823842

摘要： A method for forming an electrical device that includes forming a high-k gate dielectric layer over a semiconductor substrate that is patterned to separate a first portion of the high-k gate dielectric layer that is present on a first conductivity device region from a second portion of the high-k gate dielectric layer that is present on a second conductivity device region. A connecting gate conductor is formed on the first portion and the second portion of the high-k gate dielectric layer. The connecting gate conductor extends from the first conductivity device region over the isolation region to the second conductivity device region. One of the first conductivity device region and the second conductivity device region may then be exposed to an oxygen containing atmosphere. Exposure with the oxygen containing atmosphere modifies a threshold voltage of the semiconductor device that is exposed.

公开(公告)号：US08933515B2

公开(公告)日：2015-01-13

申请号：US13531175

申请日：2012-06-22

申请人： Stephen W. Bedell ,  Huiming Bu ,  Kangguo Cheng ,  Bruce B. Doris ,  Johnathan E. Faltermeier ,  Ali Khakifirooz ,  Devendra K. Sadana ,  Chun-Chen Yeh

发明人： Stephen W. Bedell ,  Huiming Bu ,  Kangguo Cheng ,  Bruce B. Doris ,  Johnathan E. Faltermeier ,  Ali Khakifirooz ,  Devendra K. Sadana ,  Chun-Chen Yeh

IPC分类号： H01L27/088 ,  H01L21/8238 ,  H01L27/02 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L21/823807 ,  H01L21/823814 ,  H01L27/0207 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/78 ,  H01L29/7843 ,  H01L29/7848

摘要： A semiconductor device and method for fabricating a semiconductor device include providing a strained semiconductor layer having a first strained axis, forming an active region within a surface of the strained semiconductor layer where the active region has a longitudinal axis along the strained axis and forming gate structures over the active region. Raised source/drain regions are formed on the active regions above and over the surface of the strained semiconductor layer and adjacent to the gate structures to form transistor devices.

摘要翻译： 一种用于制造半导体器件的半导体器件和方法包括提供具有第一应变轴的应变半导体层，在应变半导体层的表面内形成有源区，其中有源区具有沿应变轴的纵向轴线并形成栅极结构 在活跃地区。 在应变半导体层的表面上方和与栅极结构相邻的有源区上形成升高的源/漏区，以形成晶体管器件。