公开(公告)号：US08551838B2

公开(公告)日：2013-10-08

申请号：US13064559

申请日：2011-03-31

申请人： Masaru Kito ,  Hideaki Aochi ,  Ryota Katsumata ,  Akihiro Nitayama ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Yoshiaki Fukuzumi ,  Yasuyuki Matsuoka ,  Mitsuru Sato

发明人： Masaru Kito ,  Hideaki Aochi ,  Ryota Katsumata ,  Akihiro Nitayama ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Yoshiaki Fukuzumi ,  Yasuyuki Matsuoka ,  Mitsuru Sato

IPC分类号： H01L21/336 ,  H01L21/3205 ,  H01L21/4763

CPC分类号： H01L27/11582 ,  G11C16/0483 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11556 ,  H01L27/11573 ,  H01L27/11578

摘要： A nonvolatile semiconductor memory device that have a new structure are provided, in which memory cells are laminated in a three dimensional state so that the chip area may be reduced. The nonvolatile semiconductor memory device of the present invention is a nonvolatile semiconductor memory device that has a plurality of the memory strings, in which a plurality of electrically programmable memory cells is connected in series. The memory strings comprise a pillar shaped semiconductor; a first insulation film formed around the pillar shaped semiconductor; a charge storage layer formed around the first insulation film; the second insulation film formed around the charge storage layer; and first or nth electrodes formed around the second insulation film (n is natural number more than 1). The first or nth electrodes of the memory strings and the other first or nth electrodes of the memory strings are respectively the first or nth conductor layers that are spread in a two dimensional state.

摘要翻译： 提供了具有新结构的非易失性半导体存储器件，其中以三维状态层叠存储单元，从而可以减小芯片面积。 本发明的非易失性半导体存储装置是具有串联连接有多个电可编程存储单元的多个存储串的非易失性半导体存储装置。 存储器串包括柱形半导体; 形成在柱状半导体周围的第一绝缘膜; 形成在所述第一绝缘膜周围的电荷存储层; 形成在电荷存储层周围的第二绝缘膜; 并且形成在第二绝缘膜周围的第一或第n电极（n是大于1的自然数）。 存储器串的第一或第n电极和存储器串的其它第一或第n电极分别是以二维状态扩展的第一或第n导体层。

公开(公告)号：US08237211B2

公开(公告)日：2012-08-07

申请号：US12556242

申请日：2009-09-09

申请人： Yoshiaki Fukuzumi ,  Ryota Katsumata ,  Masaru Kito ,  Hiroyasu Tanaka ,  Masaru Kidoh ,  Yosuke Komori ,  Megumi Ishiduki ,  Akihiro Nitayama ,  Hideaki Aochi ,  Hitoshi Ito ,  Yasuyuki Matsuoka

发明人： Yoshiaki Fukuzumi ,  Ryota Katsumata ,  Masaru Kito ,  Hiroyasu Tanaka ,  Masaru Kidoh ,  Yosuke Komori ,  Megumi Ishiduki ,  Akihiro Nitayama ,  Hideaki Aochi ,  Hitoshi Ito ,  Yasuyuki Matsuoka

IPC分类号： H01L29/788

CPC分类号： H01L27/11578 ,  H01L27/11565 ,  H01L27/11582

摘要： A non-volatile semiconductor storage device has a memory string including a plurality of electrically rewritable memory cells connected in series. The non-volatile semiconductor storage device also has a protruding layer formed to protrude upward with respect to a substrate. The memory string includes: a plurality of first conductive layers laminated on the substrate; a first semiconductor layer formed to penetrate the plurality of first conductive layers; and an electric charge storage layer formed between the first conductive layers and the first semiconductor layer, and configured to be able to store electric charges. Each of the plurality of first conductive layers includes: a bottom portion extending in parallel to the substrate; and a side portion extending upward with respect to the substrate along the protruding layer at the bottom portion. The protruding layer has a width in a first direction parallel to the substrate that is less than or equal to its length in a lamination direction.

摘要翻译： 非易失性半导体存储装置具有串联连接的多个电可重写存储单元的存储串。 非挥发性半导体存储装置还具有形成为相对于基板向上突出的突出层。 存储器串包括：层叠在基板上的多个第一导电层; 形成为穿透所述多个第一导电层的第一半导体层; 以及形成在第一导电层和第一半导体层之间的电荷存储层，并且能够存储电荷。 多个第一导电层中的每一个包括：平行于基板延伸的底部; 以及沿底部的突出层相对于基板向上延伸的侧部。 该突出层在平行于基板的第一方向上的宽度小于或等于其在层叠方向上的长度。

公开(公告)号：US20110287597A1

公开(公告)日：2011-11-24

申请号：US13064559

申请日：2011-03-31

申请人： Masaru Kito ,  Hideaki Aochi ,  Ryota Katsumata ,  Akihiro Nitayama ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Yoshiaki Fukuzumi ,  Yasuyuki Matsuoka ,  Mitsuru Sato

发明人： Masaru Kito ,  Hideaki Aochi ,  Ryota Katsumata ,  Akihiro Nitayama ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Yoshiaki Fukuzumi ,  Yasuyuki Matsuoka ,  Mitsuru Sato

IPC分类号： H01L29/788

CPC分类号： H01L27/11582 ,  G11C16/0483 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11556 ,  H01L27/11573 ,  H01L27/11578

摘要： A nonvolatile semiconductor memory device that have a new structure are provided, in which memory cells are laminated in a three dimensional state so that the chip area may be reduced. The nonvolatile semiconductor memory device of the present invention is a nonvolatile semiconductor memory device that has a plurality of the memory strings, in which a plurality of electrically programmable memory cells is connected in series. The memory strings comprise a pillar shaped semiconductor; a first insulation film formed around the pillar shaped semiconductor; a charge storage layer formed around the first insulation film; the second insulation film formed around the charge storage layer; and first or nth electrodes formed around the second insulation film (n is natural number more than 1). The first or nth electrodes of the memory strings and the other first or nth electrodes of the memory strings are respectively the first or nth conductor layers that are spread in a two dimensional state.

摘要翻译： 提供了具有新结构的非易失性半导体存储器件，其中以三维状态层叠存储单元，从而可以减小芯片面积。 本发明的非易失性半导体存储装置是具有串联连接有多个电可编程存储单元的多个存储串的非易失性半导体存储装置。 存储器串包括柱形半导体; 形成在柱状半导体周围的第一绝缘膜; 形成在所述第一绝缘膜周围的电荷存储层; 形成在电荷存储层周围的第二绝缘膜; 并且形成在第二绝缘膜周围的第一或第n电极（n是大于1的自然数）。 存储器串的第一或第n电极和存储器串的其它第一或第n电极分别是以二维状态扩展的第一或第n导体层。

公开(公告)号：US07977738B2

公开(公告)日：2011-07-12

申请号：US12497010

申请日：2009-07-02

申请人： Yoshihiro Minami ,  Takashi Ohsawa ,  Tomoaki Shino ,  Takeshi Hamamoto ,  Akihiro Nitayama

发明人： Yoshihiro Minami ,  Takashi Ohsawa ,  Tomoaki Shino ,  Takeshi Hamamoto ,  Akihiro Nitayama

IPC分类号： H01L29/76 ,  H01L29/94

CPC分类号： H01L27/1022 ,  G11C2211/4016 ,  H01L27/108 ,  H01L27/10802 ,  H01L29/7841

摘要： A semiconductor memory device includes bodies electrically floating; sources; drains; gate electrodes, each of which is adjacent to one side surface of the one of the bodies via a gate dielectric film; plates, each of which is adjacent to the other side surface of the one of the bodies via a plate dielectric film; first bit lines on the drains, the first bit lines including a semiconductor with a same conductivity type as that of the drains; and emitters on the semiconductor of the first bit lines, the emitters including a semiconductor with an opposite conductivity type to that of the semiconductor of the first bit lines, wherein the emitters are stacked above the bodies and the drains.

摘要翻译： 半导体存储器件包括电漂浮体; 来源 下水道 栅电极，其每一个经由栅极电介质膜与所述一个主体的一个侧表面相邻; 板，其每一个经由板电介质膜与所述一个主体的另一侧表面相邻; 排水口上的第一位线，第一位线包括具有与排水管相同的导电类型的半导体; 和在第一位线的半导体上的发射极，发射器包括与第一位线的半导体的导电类型相反的导电类型的半导体，其中发射体堆叠在主体和漏极之上。

公开(公告)号：US20100172189A1

公开(公告)日：2010-07-08

申请号：US12620986

申请日：2009-11-18

申请人： Kiyotaro Itagaki ,  Yoshihisa Iwata ,  Hiroyasu Tanaka ,  Masaru Kidoh ,  Masaru Kito ,  Ryota Katsumata ,  Hideaki Aochi ,  Akihiro Nitayama ,  Takashi Maeda ,  Tomoo Hishida

发明人： Kiyotaro Itagaki ,  Yoshihisa Iwata ,  Hiroyasu Tanaka ,  Masaru Kidoh ,  Masaru Kito ,  Ryota Katsumata ,  Hideaki Aochi ,  Akihiro Nitayama ,  Takashi Maeda ,  Tomoo Hishida

IPC分类号： G11C16/04 ,  G11C7/06

CPC分类号： G11C16/0483 ,  G11C16/08 ,  G11C16/16 ,  G11C16/26 ,  G11C16/30

摘要： A non-volatile semiconductor storage device includes: a memory string including a plurality of memory cells connected in series; a first selection transistor having one end connected to one end of the memory string; a first wiring having one end connected to the other end of the first selection transistor; a second wiring connected to a gate of the first selection transistor. A control circuit is configured to boost voltages of the second wiring and the first wiring in the erase operation, while keeping the voltage of the first wiring greater than the voltage of the second wiring by a certain potential difference. The certain potential difference is a potential difference that causes a GIDL current.

摘要翻译： 非易失性半导体存储装置包括：包括串联连接的多个存储单元的存储串; 第一选择晶体管，其一端连接到存储器串的一端; 第一布线，其一端连接到第一选择晶体管的另一端; 连接到第一选择晶体管的栅极的第二布线。 控制电路被配置为在保持第一布线的电压大于第二布线的电压一定电位差的同时，在擦除操作中提高第二布线和第一布线的电压。 一定的电位差是导致GIDL电流的电位差。

公开(公告)号：US06232822B1

公开(公告)日：2001-05-15

申请号：US08268728

申请日：1994-06-30

申请人： Koji Sakui ,  Takehiro Hasegawa ,  Shigeyoshi Watanabe ,  Fujio Masuoka ,  Tsuneaki Fuse ,  Toshiki Seshita ,  Seiichi Aritome ,  Akihiro Nitayama ,  Fumio Horiguchi

发明人： Koji Sakui ,  Takehiro Hasegawa ,  Shigeyoshi Watanabe ,  Fujio Masuoka ,  Tsuneaki Fuse ,  Toshiki Seshita ,  Seiichi Aritome ,  Akihiro Nitayama ,  Fumio Horiguchi

IPC分类号： H03K17687

CPC分类号： H01L27/1025 ,  G11C11/39 ,  H01L29/36 ,  H01L29/42304 ,  H01L29/456 ,  H01L29/73 ,  H01L29/7322 ,  H01L29/885 ,  H03F3/04 ,  H03K3/021 ,  H03K17/567

摘要： A semiconductor device includes a bipolar transistor whose emitter-collector voltage is set to satisfy a condition IBE

摘要翻译： 半导体器件包括双极晶体管，其发射极 - 集电极电压被设置为满足条件IBE

公开(公告)号：US5234780A

公开(公告)日：1993-08-10

申请号：US467149

申请日：1990-01-18

申请人： Akihiro Nitayama ,  Makoto Nakase ,  Kouji Hashimoto ,  Hirotsugu Wada

发明人： Akihiro Nitayama ,  Makoto Nakase ,  Kouji Hashimoto ,  Hirotsugu Wada

IPC分类号： G03F1/00

CPC分类号： G03F1/29

摘要： An exposure mask for lithography, a method of manufacturing the same, and an exposure method using the same are disclosed. A light-transmitting opening of the exposure mask has a main light-transmitting region located in the middle of the opening and having a first optical path length, and phase shift regions adjacent to a light-shielding layer and having a second optical path length, different from the first optical path length. Light transmitted through each phase shift region interferes with light transmitted through the main light-transmitting region at the edges of the light-transmitting opening, thus enabling a sharp photo-intensity distribution of total transmitted light to be obtained. As a result, the resolution of the exposure mask is improved.

公开(公告)号：US5144579A

公开(公告)日：1992-09-01

申请号：US578608

申请日：1990-09-07

申请人： Naoko Okabe ,  Satoshi Inoue ,  Kazumasa Sunouchi ,  Takashi Yamada ,  Akihiro Nitayama ,  Hiroshi Takato

发明人： Naoko Okabe ,  Satoshi Inoue ,  Kazumasa Sunouchi ,  Takashi Yamada ,  Akihiro Nitayama ,  Hiroshi Takato

IPC分类号： H01L27/04 ,  H01L21/28 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108

CPC分类号： H01L27/10852 ,  H01L27/10808

摘要： A semiconductor memory device wherein at least one of a storage node contact hole and a bit line contact hole includes a first contact hole made in a first inter-layer insulating film formed over a gate electrode and a second contact hole made in a second inter-layer insulating film formed over an electrically conductive material embedded up to a level higher than the gate electrode in the first contact hole which is contacted with the electrically conductive material, the conductive material being exposed by etching a part of the second inter-layer insulating film, whereby the size of the memory device can be made small and the reliability can be improved. Further, a capacitor is formed in a layer higher than a bit line thereby to facilitate the processing of a storage node electrode to increase the capacitor area and to improve the reliability since it is unnecessary to carry out patterning a plate electrode within a cell array. With the above construction, a short-circuiting between the embedded layers is removed and a good quality of the second inter-layer insulating film is formed.

摘要翻译： 一种半导体存储器件，其中存储节点接触孔和位线接触孔中的至少一个包括在形成在栅电极上的第一层间绝缘膜中形成的第一接触孔和在第二互连孔中形成的第二接触孔， 在导电材料上形成的层间绝缘膜，该导电材料在与导电材料接触的第一接触孔中嵌入高于栅电极的电平，通过蚀刻第二层间绝缘膜的一部分而露出导电材料 从而可以使存储器件的尺寸小并且可以提高可靠性。 此外，在高于位线的层中形成电容器，从而不需要对单元阵列内的平板电极进行图案化，便于存储节点电极的处理以增加电容器面积并提高可靠性。 利用上述结构，去除了嵌入层之间的短路，形成了第二层间绝缘膜的良好质量。

公开(公告)号：US5138412A

公开(公告)日：1992-08-11

申请号：US636556

申请日：1991-01-07

申请人： Katsuhiko Hieda ,  Akihiro Nitayama ,  Fumio Horiguchi

发明人： Katsuhiko Hieda ,  Akihiro Nitayama ,  Fumio Horiguchi

IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108

CPC分类号： H01L27/10852 ,  H01L27/10817

摘要： A dynamic RAM comprises a semiconductor substrate, first and second MOS transistor formed on said semiconductor substrate, each having a source, a drain, and a gate, a first insulation film formed on said first and second MOS transistors, a first electrode formed on said first insulation film, for accumulating an electrical charge, the first electrode extending through a first hole made in the first insulation film and connected to one of the source and drain of said first MOS transistor, a second electrode formed on the first insulation film, for accumulating an electrical charge, the second electrode extending through a second hole made in the first insulation film and connected to one of the source and drain of the second MOS transistor, and at least one part of the second electrode being spaced apart from, located above, and overlapping part of the first electrode, first and second capacitor-insulating films formed on the first and second electrodes, respectively, and a capacitor electrode fromed on the first and second capacitor-insulating films and having a portion interposed between the overlapping parts of the first and second electrodes.

摘要翻译： 动态RAM包括形成在所述半导体衬底上的半导体衬底，每个具有源极，漏极和栅极的第一和第二MOS晶体管，形成在所述第一和第二MOS晶体管上的第一绝缘膜，形成在所述第一和第二MOS晶体管上的第一电极， 第一绝缘膜，用于累积电荷，所述第一电极延伸穿过由所述第一绝缘膜制成的第一孔并连接到所述第一MOS晶体管的源极和漏极中的一个，形成在所述第一绝缘膜上的第二电极，用于 累积电荷，所述第二电极延伸通过在所述第一绝缘膜中制成的第二孔并且连接到所述第二MOS晶体管的源极和漏极中的一个，并且所述第二电极的至少一部分与所述第二绝缘膜上的 以及分别形成在第一和第二电极上的第一电极，第一和第二电容器绝缘膜的重叠部分，以及电容器e 在第一和第二电容器绝缘膜上引导，并且具有插入在第一和第二电极的重叠部分之间的部分。

公开(公告)号：US5106774A

公开(公告)日：1992-04-21

申请号：US650992

申请日：1991-02-04

申请人： Katsuhiko Hieda ,  Fumio Horiguchi ,  Takeshi Hamamoto ,  Akihiro Nitayama ,  Kazumasa Sunouchi ,  Kei Kurosawa ,  Fujio Masuoka

发明人： Katsuhiko Hieda ,  Fumio Horiguchi ,  Takeshi Hamamoto ,  Akihiro Nitayama ,  Kazumasa Sunouchi ,  Kei Kurosawa ,  Fujio Masuoka

IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108

CPC分类号： H01L27/10861 ,  H01L27/10829

摘要： A dynamic random access memory is disclosed which includes a trench type memory cell having a transistor formed in a semiconductive substrate, and a capacitor arranged in a trench formed in the substrate and having a trench structure. The capacitor includes an impurity-doped semiconductive layer formed on the substrate so as to surround the trench and having a conductivity type opposite to that of the substrate, a first capacitor electrode formed in the trench, and a second capacitor electrode having a portion insulatively stacked with said first capacitor electrode in the trench.

摘要翻译： 公开了一种动态随机存取存储器，其包括具有形成在半导体衬底中的晶体管的沟槽型存储单元和布置在形成在衬底中并具有沟槽结构的沟槽中的电容器。 电容器包括形成在衬底上的杂质掺杂半导体层，以围绕沟槽并且具有与衬底的导电类型相反的导电类型，形成在沟槽中的第一电容器电极和具有绝缘层叠的部分的第二电容器电极 所述第一电容器电极在沟槽中。