公开(公告)号：US08498144B2

公开(公告)日：2013-07-30

申请号：US13191678

申请日：2011-07-27

申请人： Masahiro Takahashi ,  Katsuyuki Fujita ,  Yoshihiro Ueda ,  Katsuhiko Hoya

发明人： Masahiro Takahashi ,  Katsuyuki Fujita ,  Yoshihiro Ueda ,  Katsuhiko Hoya

IPC分类号： G11C11/00 ,  G11C11/15

CPC分类号： G11C8/10 ,  G11C8/08 ,  G11C11/1675 ,  G11C11/1693

摘要： A semiconductor storage device includes first to fourth switch circuit. The semiconductor storage device includes a row decoder which controls a voltage of a word line. The semiconductor storage device includes a first selection transistor of which a control terminal is connected to the word line. The semiconductor storage device includes a first resistance change element which is connected in series to the first selection transistor between the first bit line and the second bit line, and of which a resistance value changes according to a flowing current. The semiconductor storage device includes a second selection transistor of which a control terminal is connected to the word line. The semiconductor storage device includes a second resistance change element which is connected in series to the second selection transistor between the second bit line and the third bit line, and of which a resistance value changes according to a flowing current.

摘要翻译： 半导体存储装置包括第一至第四开关电路。 半导体存储装置包括用于控制字线电压的行译码器。 半导体存储装置包括控制端子连接到字线的第一选择晶体管。 半导体存储装置包括与第一位线和第二位线之间的第一选择晶体管串联连接的第一电阻变化元件，其电阻值根据流动电流而变化。 半导体存储装置包括控制端子连接到字线的第二选择晶体管。 半导体存储装置包括与第二位线和第三位线之间的第二选择晶体管串联连接的第二电阻变化元件，其电阻值根据流动电流而变化。

公开(公告)号：US20120243297A1

公开(公告)日：2012-09-27

申请号：US13428312

申请日：2012-03-23

申请人： Akira KATAYAMA ,  Yoshihiro Ueda

发明人： Akira KATAYAMA ,  Yoshihiro Ueda

IPC分类号： G11C11/00

CPC分类号： G11C11/161 ,  G11C11/1655 ,  G11C11/1659 ,  G11C11/1673 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0061 ,  G11C13/0069 ,  G11C2013/0073

摘要： According to one embodiment, a resistance change type memory includes first to third bit lines, a word line and a memory cell connected to the first to third bit lines and the word line. The memory cell includes a first transistor and a first memory element between the first and third bit lines, a second transistor and a second memory element between the second and third bit lines. Control terminals of the first and second transistors are connected to the word line. The resistance states of the first and second memory elements change to the first or second resistance state in accordance with a write pulse.

摘要翻译： 根据一个实施例，电阻变化型存储器包括第一至第三位线，字线和连接到第一至第三位线和字线的存储单元。 存储单元包括第一和第三位线之间的第一晶体管和第一存储元件，第二晶体管和第二位线之间的第二存储元件。 第一和第二晶体管的控制端连接到字线。 根据写入脉冲，第一和第二存储元件的电阻状态变为第一或第二电阻状态。

公开(公告)号：US20120063215A1

公开(公告)日：2012-03-15

申请号：US13191678

申请日：2011-07-27

申请人： Masahiro TAKAHASHI ,  Katsuyuki Fujita ,  Yoshihiro Ueda ,  Katsuhiko Hoya

发明人： Masahiro TAKAHASHI ,  Katsuyuki Fujita ,  Yoshihiro Ueda ,  Katsuhiko Hoya

IPC分类号： G11C11/00

CPC分类号： G11C8/10 ,  G11C8/08 ,  G11C11/1675 ,  G11C11/1693

摘要： A semiconductor storage device includes first to fourth switch circuit. The semiconductor storage device includes a row decoder which controls a voltage of a word line. The semiconductor storage device includes a first selection transistor of which a control terminal is connected to the word line. The semiconductor storage device includes a first resistance change element which is connected in series to the first selection transistor between the first bit line and the second bit line, and of which a resistance value changes according to a flowing current. The semiconductor storage device includes a second selection transistor of which a control terminal is connected to the word line. The semiconductor storage device includes a second resistance change element which is connected in series to the second selection transistor between the second bit line and the third bit line, and of which a resistance value changes according to a flowing current.

摘要翻译： 半导体存储装置包括第一至第四开关电路。 半导体存储装置包括用于控制字线电压的行译码器。 半导体存储装置包括控制端子连接到字线的第一选择晶体管。 半导体存储装置包括与第一位线和第二位线之间的第一选择晶体管串联连接的第一电阻变化元件，其电阻值根据流动电流而变化。 半导体存储装置包括控制端子连接到字线的第二选择晶体管。 半导体存储装置包括与第二位线和第三位线之间的第二选择晶体管串联连接的第二电阻变化元件，其电阻值根据流动电流而变化。

公开(公告)号：US08086570B2

公开(公告)日：2011-12-27

申请号：US11282022

申请日：2005-11-17

申请人： Shigehisa Kawabe ,  Setsu Kunitake ,  Yoshihiro Ueda ,  Kenichi Numata ,  Akira Suzuki ,  Masao Nukaga ,  Taro Terao ,  Meng Shi

发明人： Shigehisa Kawabe ,  Setsu Kunitake ,  Yoshihiro Ueda ,  Kenichi Numata ,  Akira Suzuki ,  Masao Nukaga ,  Taro Terao ,  Meng Shi

IPC分类号： G06F7/00 ,  G06F17/00

CPC分类号： G06F17/30011

摘要： The document management server includes an identification information providing unit that receives a request to obtain identification information required for accessing a document from a client, generates the identification information for the received request, and sends the generated identification information to the client; a relation information management unit that manages relation information of the requested document and the identification information generated for the request; and a history information management unit that manages information on the client who has sent the request, associating with the identification information.

摘要翻译： 文件管理服务器包括识别信息提供单元，其接收从客户端获取文档所需的识别信息的请求，生成接收到的请求的识别信息，并将生成的识别信息发送给客户端; 关系信息管理单元，其管理所请求的文档的关系信息和为该请求生成的识别信息; 以及历史信息管理单元，其管理已经发送请求的客户端的信息，与该识别信息相关联。

公开(公告)号：US08040718B2

公开(公告)日：2011-10-18

申请号：US12559311

申请日：2009-09-14

申请人： Yoshihiro Ueda

发明人： Yoshihiro Ueda

IPC分类号： G11C11/00

CPC分类号： G11C11/1653 ,  G11C11/1659 ,  G11C11/1673

摘要： A semiconductor memory device includes a memory cell having a first resistance state and a second resistance state, a bit line connected to the memory cell, a reference cell fixed to the first resistance state, a reference bit line connected to the reference cell, and a generation circuit configured to generate a reading voltage and a reference voltage. The generation circuit includes a constant current source connected to a first node, a first replica cell connected between the first node and a second node and fixed to the first resistance state, a second replica cell connected between the second node and a third node and fixed to the second resistance state, a first resistance element connected between the first node and a fourth node, and a second resistance element connected between the fourth node and the third node.

摘要翻译： 半导体存储器件包括具有第一电阻状态和第二电阻状态的存储单元，连接到存储单元的位线，固定到第一电阻状态的参考单元，连接到参考单元的参考位线，以及 所述发生电路被配置为产生读取电压和参考电压。 所述生成电路包括连接到第一节点的恒流源，连接在所述第一节点和第二节点之间并固定到所述第一电阻状态的第一副本单元，连接在所述第二节点和第三节点之间并固定的第二复制单元 连接到第二电阻状态，连接在第一节点和第四节点之间的第一电阻元件以及连接在第四节点和第三节点之间的第二电阻元件。

公开(公告)号：US20110238880A1

公开(公告)日：2011-09-29

申请号：US12771072

申请日：2010-04-30

申请人： Katsuhiro Hirayama ,  Hiroto Yoshikawa ,  Yoshihiro Ueda ,  Osamu Mikami

发明人： Katsuhiro Hirayama ,  Hiroto Yoshikawa ,  Yoshihiro Ueda ,  Osamu Mikami

IPC分类号： G06F13/00 ,  G06F13/28

CPC分类号： G06F13/385 ,  G06F2213/3804

摘要： There is provided an interface card system for SD bus control. The interface card system for SD bus control includes a CPU bus interface 11a and/or an SD bus interface 11b, a host interface module 16 connected to the interfaces which interprets an SD command and controls operation of the whole of the interface card system, first and second internal SD host engines 15a and 15b which function as a host controller, first and second selectors 14a and 14b respectively connected to the internal SD host engines which each select a path for data or a command, first and second SD bus interfaces 13a and 13b respectively connected to the selectors, and a data pass-through control section 17 connected to the SD bus interfaces connected to the selectors which allows an SD command and data to pass through.

摘要翻译： 提供了一种用于SD总线控制的接口卡系统。 用于SD总线控制的接口卡系统包括CPU总线接口11a和/或SD总线接口11b，连接到解释SD命令并控制整个接口卡系统的操作的接口的主机接口模块16 和用作主机控制器的第二内部SD主机引擎15a和15b，分别连接到内部SD主机引擎的第一和第二选择器14a和14b，每个内部SD主机引擎选择数据或命令的路径，第一和第二SD总线接口13a和 13b，以及连接到连接到选择器的SD总线接口的数据传递控制部分17，其允许SD命令和数据通过。

公开(公告)号：US07966842B2

公开(公告)日：2011-06-28

申请号：US12604213

申请日：2009-10-22

申请人： Toyoshi Kamisako ,  Yoshihiro Ueda ,  Kazuya Nakanishi ,  Tadashi Adachi ,  Kazuyuki Hamada ,  Kiyotaka Tabira ,  Yasuyuki Okamoto ,  Kenichi Okabe ,  Masashi Yuasa ,  Kenichi Kakita ,  Kiyoshi Mori ,  Tosiaki Mamemoto ,  Katsunori Horii

发明人： Toyoshi Kamisako ,  Yoshihiro Ueda ,  Kazuya Nakanishi ,  Tadashi Adachi ,  Kazuyuki Hamada ,  Kiyotaka Tabira ,  Yasuyuki Okamoto ,  Kenichi Okabe ,  Masashi Yuasa ,  Kenichi Kakita ,  Kiyoshi Mori ,  Tosiaki Mamemoto ,  Katsunori Horii

IPC分类号： F25D17/02

CPC分类号： F25D17/042 ,  A23L3/3409 ,  A23L3/363 ,  F25D2317/0413

摘要： The refrigerator includes a vegetable compartment (107) thermally insulated by a rear partition (111), and a mist generation department (139) for atomizing a mist into the vegetable compartment (107), and the mist generation department (139) includes a atomizing electrode (135) for atomizing the mist into the vegetable compartment (107), a voltage applicator (133) for applying a voltage to the atomizing electrode (135), and a cooling pin (134) coupled to the atomizing electrode (135), in which the atomizing electrode (135) is cooled to a temperature lower than the dew point by a outlet air-duct for freezer compartment (141), and the moisture in the air is cooled to condense dew on the atomizing electrode (135), and is atomized as a mist into the vegetable compartment (107), and dew can be condensed from moisture onto the atomizing electrode (135) stably and in a simple configuration, and the freshness of the food is enhanced while the reliability of the refrigerator is enhanced.

摘要翻译： 冰箱包括通过后隔板（111）隔热的蔬菜室（107）和用于将雾雾化到蔬菜室（107）中的雾化部（139），雾生成部（139）包括雾化 用于将雾雾化到蔬菜室（107）中的电极（135），用于向雾化电极（135）施加电压的电压施加器（133）和耦合到雾化电极（135）的冷却销（134） 其中雾化电极（135）通过冷冻室（141）的出口空气导管冷却到低于露点的温度，并且空气中的水分被冷却以使雾化电极（135）上的露水冷凝， 并且被雾化成蔬菜室107，能够以简单的结构将湿气从湿气中冷凝到雾化电极135上，并且能够提高食品的新鲜度，同时冰箱的可靠性为 增强。

公开(公告)号：US07916522B2

公开(公告)日：2011-03-29

申请号：US12400262

申请日：2009-03-09

申请人： Kiyotaro Itagaki ,  Tsuneo Inaba ,  Yoshihiro Ueda ,  Yoshiaki Asao

发明人： Kiyotaro Itagaki ,  Tsuneo Inaba ,  Yoshihiro Ueda ,  Yoshiaki Asao

IPC分类号： G11C11/15

CPC分类号： G11C11/5607 ,  G11C11/161 ,  G11C11/1659 ,  G11C11/1675 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/003 ,  G11C13/0061 ,  G11C13/0069 ,  G11C2013/0078 ,  G11C2013/0092 ,  G11C2213/75 ,  G11C2213/78

摘要： A semiconductor memory device includes n resistance change elements which are arranged in one cell, have a low-resistance state and a high resistance state, are connected in series or parallel, have different resistance values in the same resistance state, and change between the low-resistance state and the high-resistance state under different conditions, and a write circuit which is connected to one end of the n resistance change elements, and applies a pulse current m (1≦m≦n) times to the n resistance change elements during a write operation. Letting Im be a current value of an mth pulse current, condition I1>I2> . . . >Im holds.

摘要翻译： 半导体存储器件包括在一个单元中布置的具有低电阻状态和高电阻状态的n个电阻变化元件串联或并联连接，在相同电阻状态下具有不同的电阻值，并且在低电平 电阻状态和不同条件下的高电阻状态，以及与n个电阻变化元件的一端连接的写入电路，并向n个电阻变化元件施加脉冲电流m（1＆nlE; m＆nlE; n）次 在写操作期间。 令Im为第m个脉冲电流的当前值，条件I1> I2>。 。 。 > Im持有。

公开(公告)号：US20100236269A1

公开(公告)日：2010-09-23

申请号：US12741718

申请日：2008-11-05

申请人： Tosiaki Mamemoto ,  Toyoshi Kamisako ,  Yoshihiro Ueda ,  Katsunori Horii ,  Kenichi Kakita ,  Tadashi Adachi ,  Kahoru Tsujimoto ,  Kiyoshi Mori

发明人： Tosiaki Mamemoto ,  Toyoshi Kamisako ,  Yoshihiro Ueda ,  Katsunori Horii ,  Kenichi Kakita ,  Tadashi Adachi ,  Kahoru Tsujimoto ,  Kiyoshi Mori

IPC分类号： F25D31/00 ,  B05B5/025

CPC分类号： F25D17/042 ,  A23B7/0425 ,  A23B7/055 ,  A23B7/144 ,  A23L3/364 ,  A23L3/375 ,  B05B5/0255 ,  B05B5/0533 ,  B05B5/057 ,  B05B7/0012 ,  F25D29/00 ,  F25D2317/0413 ,  F25D2317/04131 ,  F25D2600/02 ,  F25D2700/12 ,  F25D2700/14

摘要： A refrigerator that sprays a mist using an atomization apparatus includes an atomization state determination unit that determines an atomization state of an atomization unit. An operation of the atomization unit is controlled according to a signal determined by the atomization state determination unit. Thus, an appropriate amount of mist spray is performed according to the atomization state, so that improved spray accuracy can be attained.

摘要翻译： 使用雾化装置喷雾的冰箱包括确定雾化单元的雾化状态的雾化状态判定单元。 根据由雾化状态确定单元确定的信号来控制雾化单元的操作。 因此，根据雾化状态进行适当量的喷雾，从而可以获得提高的喷雾精度。

公开(公告)号：US07649792B2

公开(公告)日：2010-01-19

申请号：US11749412

申请日：2007-05-16

申请人： Yoshihiro Ueda ,  Yoshihisa Iwata ,  Toshiaki Edahiro ,  Toshihiro Suzuki

发明人： Yoshihiro Ueda ,  Yoshihisa Iwata ,  Toshiaki Edahiro ,  Toshihiro Suzuki

IPC分类号： G11C7/02

CPC分类号： G11C7/065 ,  G11C7/062 ,  G11C7/12 ,  G11C11/1673 ,  G11C16/0491 ,  G11C16/26 ,  G11C17/126 ,  G11C2207/002 ,  G11C2207/063

摘要： A sense amplifier according to an example of the present invention has first, second, third and fourth FETs with a flip-flop connection. A drain of a fifth FET is connected to a first input node, and its source is connected to a power source node. A drain of a sixth FET is connected to a second input node, and its source is connected to the power source node. A sense operation is started by charging a first output node from the first input node with a first current and by charging a second output node from the second input node with a second current. The fifth and sixth FET are turned on after starting the sense operation.

摘要翻译： 根据本发明的示例的读出放大器具有触发器连接的第一，第二，第三和第四FET。 第五FET的漏极连接到第一输入节点，并且其源极连接到电源节点。 第六FET的漏极连接到第二输入节点，其源极连接到电源节点。 通过用第一电流从第一输入节点充电第一输出节点并且通过用第二电流从第二输入节点充电第二输出节点来开始感测操作。 开始感测操作后，第五和第六FET导通。