公开(公告)号：US06713790B2

公开(公告)日：2004-03-30

申请号：US10212799

申请日：2002-08-07

申请人： Akira Asai ,  Teruhito Oonishi ,  Takeshi Takagi ,  Tohru Saitoh ,  Yoshihiro Hara ,  Koichiro Yuki ,  Katsuya Nozawa ,  Yoshihiko Kanzawa ,  Koji Katayama ,  Yo Ichikawa

发明人： Akira Asai ,  Teruhito Oonishi ,  Takeshi Takagi ,  Tohru Saitoh ,  Yoshihiro Hara ,  Koichiro Yuki ,  Katsuya Nozawa ,  Yoshihiko Kanzawa ,  Koji Katayama ,  Yo Ichikawa

IPC分类号： H01L31072

CPC分类号： H01L29/66242 ,  H01L21/763 ,  H01L21/8249 ,  H01L27/0623 ,  H01L29/7378

摘要： In the method for fabricating a semiconductor device of the present invention, a collector layer of a first conductivity type is formed in a region of a semiconductor substrate sandwiched by device isolation. A collector opening is formed through a first insulating layer deposited on the semiconductor substrate so that the range of the collector opening covers the collector layer and part of the device isolation. A semiconductor layer of a second conductivity type as an external base is formed on a portion of the semiconductor substrate located inside the collector opening, while junction leak prevention layers of the same conductivity type as the external base are formed in the semiconductor substrate. Thus, the active region is narrower than the collector opening reducing the transistor area, while minimizing junction leak.

摘要翻译： 在本发明的半导体装置的制造方法中，在被器件分离夹持的半导体基板的区域中形成有第一导电型的集电极层。 通过沉积在半导体衬底上的第一绝缘层形成集电极开口，使得集电极开口的范围覆盖集电极层和器件隔离的一部分。 在位于集电体开口内部的半导体基板的一部分上形成作为外部基底的第二导电类型的半导体层，同时在半导体衬底中形成与外部基底相同的导电类型的防漏层。 因此，有源区域比集电极开口窄，减小晶体管面积，同时最小化结漏电。

公开(公告)号：US08675393B2

公开(公告)日：2014-03-18

申请号：US13636258

申请日：2011-03-18

申请人： Koji Katayama ,  Takeshi Takagi ,  Mitsuteru Iijima

发明人： Koji Katayama ,  Takeshi Takagi ,  Mitsuteru Iijima

IPC分类号： G11C11/00

CPC分类号： G11C13/0007 ,  G11C2213/72 ,  H01L27/2409 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1625

摘要： Provided is a method for driving a non-volatile memory element in which a variable resistance element including a first electrode, a second electrode, and a variable resistance layer capable of reversibly changing between a high resistance state and a low resistance state with application of electrical signals having different polarities is connected in series with a current steering element having bidirectional rectifying characteristics with respect to an applied voltage. After the non-volatile memory element is manufactured, the resistance value of the variable resistance layer is reduced from a resistance value in the initial resistance state higher than that in the high resistance state by applying, to the non-volatile memory element, a voltage pulse having the polarity identical to that of the voltage pulse for changing the variable resistance layer from the low resistance state to the high resistance state in the normal operations.

摘要翻译： 提供一种用于驱动非易失性存储元件的方法，其中包括第一电极，第二电极和可变电阻层的可变电阻元件，所述可变电阻元件能够通过施加电而在高电阻状态和低电阻状态之间可逆地变化 具有不同极性的信号与具有相对于施加电压的双向整流特性的电流导向元件串联连接。 在制造非易失性存储元件之后，通过向非易失性存储元件施加电压，可变电阻层的电阻值比初始电阻状态中的电阻值高于高电阻状态的电阻值 脉冲具有与用于在正常操作中将可变电阻层从低电阻状态改变为高电阻状态的电压脉冲的极性相同的脉冲。

公开(公告)号：US20130314975A1

公开(公告)日：2013-11-28

申请号：US13983855

申请日：2012-02-07

申请人： Koji Katayama ,  Takeshi Takagi

发明人： Koji Katayama ,  Takeshi Takagi

IPC分类号： G11C13/00

CPC分类号： G11C13/0069 ,  G11C13/0007 ,  G11C13/004 ,  G11C29/50008 ,  G11C2013/0045 ,  G11C2013/0083 ,  G11C2213/72 ,  H01L27/101 ,  H01L27/1021 ,  H01L27/2409 ,  H01L27/2418 ,  H01L28/20 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/146

摘要： A method for programming a nonvolatile memory element includes: decreasing a resistance value of a variable resistance element in an initial state, by applying an initialization voltage pulse to a series circuit in which a load resistor having a first resistance value is connected in series with the variable resistance element and a MSM diode; applying, after the decreasing, a write voltage pulse to the series circuit after the resistance value of the variable resistance element is changed to a second resistance value lower than the first resistance value; and applying, after the decreasing, an erase voltage pulse to the series circuit after the resistance value of the variable resistance element is changed to a third resistance value lower than the first resistance value.

摘要翻译： 一种用于非易失性存储元件的编程方法包括：通过向串联电路施加初始化电压脉冲来降低初始状态下的可变电阻元件的电阻值，其中具有第一电阻值的负载电阻器与 可变电阻元件和MSM二极管; 在可变电阻元件的电阻值变为低于第一电阻值的第二电阻值之后，在减小之后向串联电路施加写入电压脉冲; 以及在所述可变电阻元件的电阻值变为低于所述第一电阻值的第三电阻值之后，在所述减小之后向所述串联电路施加擦除电压脉冲。

公开(公告)号：US08508976B2

公开(公告)日：2013-08-13

申请号：US12994910

申请日：2010-04-23

申请人： Koji Katayama ,  Takeshi Takagi

发明人： Koji Katayama ,  Takeshi Takagi

IPC分类号： G11C11/00 ,  H01L45/00

CPC分类号： G11C13/003 ,  G11C13/0007 ,  G11C2213/15 ,  G11C2213/32 ,  G11C2213/34 ,  G11C2213/56 ,  G11C2213/76 ,  G11C2213/79 ,  H01L27/2409 ,  H01L27/2436 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1625 ,  H01L45/1683

摘要： Provided is a nonvolatile memory element which has a small variation in operation and allow stable operation. The nonvolatile memory element includes: a first electrode (102); a second electrode (106); a variable resistance layer (105) which is formed between the electrodes (102 and 106) and is connected to the electrodes (102 and 106), and which reversibly changes between a high resistance state and a low resistance state according to a polarity of a voltage applied between the electrodes (102 and 106); and a fixed resistance layer (104) which has a resistance value that is 0.1 and 10 times as large as a resistance value of the variable resistance layer in the high resistance state, the fixed resistance layer (104) being formed between the electrodes (102 and 106) and being electrically connected to at least a part of the variable resistance layer (105).

摘要翻译： 提供了一种非易失性存储元件，其具有小的操作变化并且允许稳定的操​​作。 非易失性存储元件包括：第一电极（102）; 第二电极（106）; 形成在所述电极（102和106）之间并连接到所述电极（102和106）的可变电阻层（105），并且根据所述电极（102和106）的极性在高电阻状态和低电阻状态之间可逆地变化 施加在电极（102和106）之间的电压; 和固定电阻层（104），其电阻值是高电阻状态下的可变电阻层的电阻值的0.1和10倍，固定电阻层（104）形成在电极（102）之间 和106），并且电连接到可变电阻层（105）的至少一部分。

公开(公告)号：US08309946B2

公开(公告)日：2012-11-13

申请号：US12935455

申请日：2009-07-22

申请人： Satoru Mitani ,  Shunsaku Muraoka ,  Yoshihiko Kanzawa ,  Koji Katayama ,  Ryoko Miyanaga ,  Satoru Fujii ,  Takeshi Takagi

发明人： Satoru Mitani ,  Shunsaku Muraoka ,  Yoshihiko Kanzawa ,  Koji Katayama ,  Ryoko Miyanaga ,  Satoru Fujii ,  Takeshi Takagi

IPC分类号： H01L47/00

CPC分类号： H01L27/101 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/1273 ,  H01L45/146 ,  H01L45/1625 ,  H01L45/1641

摘要： A resistance variable element of the present invention comprises a first electrode (103), a second electrode (107), and a resistance variable layer which is interposed between the first electrode (103) and the second electrode (107) to contact the first electrode (103) and the second electrode (107), the resistance variable layer being configured to change in response to electric signals with different polarities which are applied between the first electrode (103) and the second electrode (107), the resistance variable layer comprising an oxygen-deficient transition metal oxide layer, and the second electrode (107) comprising platinum having minute hillocks (108).

摘要翻译： 本发明的电阻可变元件包括第一电极（103），第二电极（107）和介于第一电极（103）和第二电极（107）之间的电阻变化层，以接触第一电极 （103）和第二电极（107），电阻变化层被配置为响应于施加在第一电极（103）和第二电极（107）之间的具有不同极性的电信号而改变，电阻变化层包括 氧缺乏的过渡金属氧化物层，以及包含具有分开的小丘（108）的铂的第二电极（107）。

公开(公告)号：US20120170353A1

公开(公告)日：2012-07-05

申请号：US13379463

申请日：2011-06-28

申请人： Mitsuteru Iijima ,  Takeshi Takagi ,  Koji Katayama

发明人： Mitsuteru Iijima ,  Takeshi Takagi ,  Koji Katayama

IPC分类号： G11C11/00

CPC分类号： G11C13/003 ,  G11C11/5685 ,  G11C13/0007 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2213/72 ,  G11C2213/74 ,  G11C2213/76 ,  H01L27/101 ,  H01L27/1021 ,  H01L27/2409 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/146

摘要： A method for programming a nonvolatile memory device according to the present invention includes a step of detecting an excessively low resistance cell from among a plurality of memory cells (11) (S101); a step of changing the resistance value of a load resistor (121) to a second resistance value smaller than a first resistance value (S103); and a step of causing, by applying a voltage pulse to a series circuit including the excessively low resistance cell and the load resistor (121) having the second resistance value, a variable resistance element (105) included in the excessively low resistance cell to shift to a second high resistance state having a resistance value greater than that of the first low resistance state (S104).

摘要翻译： 根据本发明的非易失性存储器件的编程方法包括从多个存储单元（11）中检测过低电阻单元的步骤（S101）; 将负载电阻器（121）的电阻值改变为小于第一电阻值的第二电阻值的步骤（S103）; 以及通过对包括过低电阻单元的串联电路和具有第二电阻值的负载电阻器（121）施加电压脉冲，使包含在过低电阻单元中的可变电阻元件（105）移位 到具有大于第一低电阻状态的电阻值的第二高电阻状态（S104）。

公开(公告)号：US06455364B1

公开(公告)日：2002-09-24

申请号：US09526686

申请日：2000-03-15

申请人： Akira Asai ,  Teruhito Oonishi ,  Takeshi Takagi ,  Tohru Saitoh ,  Yoshihiro Hara ,  Koichiro Yuki ,  Katsuya Nozawa ,  Yoshihiko Kanzawa ,  Koji Katayama ,  Yo Ichikawa

发明人： Akira Asai ,  Teruhito Oonishi ,  Takeshi Takagi ,  Tohru Saitoh ,  Yoshihiro Hara ,  Koichiro Yuki ,  Katsuya Nozawa ,  Yoshihiko Kanzawa ,  Koji Katayama ,  Yo Ichikawa

IPC分类号： H01L218249

CPC分类号： H01L29/66242 ,  H01L21/763 ,  H01L21/8249 ,  H01L27/0623 ,  H01L29/7378

摘要： In the method for fabricating a semiconductor device of the present invention, a collector layer of a first conductivity type is formed in a region of a semiconductor substrate sandwiched by device isolation. A collector opening is formed through a first insulating layer deposited on the semiconductor substrate so that the range of the collector opening covers the collector layer and part of the device isolation. A semiconductor layer of a second conductivity type as an external base is formed on a portion of the semiconductor substrate located inside the collector opening, while junction leak prevention layers of the same conductivity type as the external base are formed in the semiconductor substrate. Thus, the active region is narrower than the collector opening reducing the transistor area, while minimizing junction leak.

摘要翻译： 在本发明的半导体装置的制造方法中，在被器件分离夹持的半导体基板的区域中形成有第一导电型的集电极层。 通过沉积在半导体衬底上的第一绝缘层形成集电极开口，使得集电极开口的范围覆盖集电极层和器件隔离的一部分。 在位于集电体开口内部的半导体基板的一部分上形成作为外部基底的第二导电类型的半导体层，同时在半导体衬底中形成与外部基底相同的导电类型的防漏层。 因此，有源区域比集电极开口窄，减小晶体管面积，同时最小化结漏电。

公开(公告)号：US08796660B2

公开(公告)日：2014-08-05

申请号：US12375881

申请日：2007-09-21

申请人： Takeshi Takagi ,  Takumi Mikawa

发明人： Takeshi Takagi ,  Takumi Mikawa

IPC分类号： H01L29/02 ,  H01L47/00 ,  H01L29/04 ,  H01L29/06 ,  H01L29/08 ,  H01L31/0352 ,  H01L45/00 ,  H01L27/24 ,  H01L27/10 ,  H01L21/00 ,  G11C11/00

CPC分类号： H01L45/04 ,  H01L27/101 ,  H01L27/2409 ,  H01L27/2418 ,  H01L27/2463 ,  H01L45/1233 ,  H01L45/1273 ,  H01L45/146 ,  H01L45/1683

摘要： A nonvolatile memory element (20) of the present invention comprises a resistance variable element (14) and a diode (18) which are formed on a substrate (10) such that the resistance variable element (14) has a resistance variable layer (11) sandwiched between a lower electrode (12) and an upper electrode (13), and the diode (18) which is connected in series with the resistance variable element (14) in the laminating direction and has an insulating layer or semiconductor layer (15) sandwiched between a first electrode (16) at the lower side and a second electrode (17) at the upper side. The resistance variable layer (11) is embedded in a first contact hole (21) formed on the lower electrode (12). A first area (22) where insulating layer or semiconductor layer (15) of the diode (18) is in contact with a first electrode (16) of the diode (18) is larger than at least one of a second area (23) where the resistance variable layer (11) is in contact with the upper electrode (13) and a third area (24) where the resistance variable layer (11) is in contact with the lower electrode (12).

摘要翻译： 本发明的非易失性存储元件（20）包括形成在基板（10）上的电阻可变元件（14）和二极管（18），使得电阻可变元件（14）具有电阻变化层（11 ）和位于下电极（12）和上电极（13）之间的二极管（18），以及与电阻可变元件（14）在层叠方向上串联连接并具有绝缘层或半导体层（15）的二极管 ）夹在下侧的第一电极（16）和上侧的第二电极（17）之间。 电阻变化层（11）嵌入形成在下电极（12）上的第一接触孔（21）中。 二极管（18）的绝缘层或半导体层（15）与二极管（18）的第一电极（16）接触的第一区域（22）大于第二区域（23）中的至少一个， 其中电阻变化层（11）与上电极（13）接触，电阻变化层（11）与下电极（12）接触的第三区域（24）。

公开(公告)号：US08712702B2

公开(公告)日：2014-04-29

申请号：US13167585

申请日：2011-06-23

申请人： Takeshi Takagi ,  Koji Okumura ,  Tatsuo Kamata

发明人： Takeshi Takagi ,  Koji Okumura ,  Tatsuo Kamata

IPC分类号： G06F19/00 ,  G01N1/10

CPC分类号： G01N1/38 ,  B01L3/502715 ,  B01L2200/10 ,  B01L2300/0654 ,  B01L2300/0816 ,  B01L2300/087 ,  B01L2300/0877 ,  B01L2300/0883 ,  B01L2300/0887 ,  B01L2400/0406 ,  G01N27/3271 ,  G01N2021/054 ,  G01N2035/1018

摘要： A measuring apparatus for measuring a predetermined physical property of a liquid measuring sample comprises a preparing unit in which a plurality of materials including at least a liquid material are mixed; a supply route which supplies the liquid material to the preparing unit; a withdrawing unit which withdraws the measuring sample from the preparing unit into the supply route, the measuring sample being prepared to contain the liquid material supplied to the preparing unit via the supply route; and a measuring unit which measures the predetermined physical property of the measuring sample withdrawn into the supply route by the withdrawing unit.

摘要翻译： 用于测量液体测量样品的预定物理性能的测量装置包括其中混合至少包含液体材料的多种材料的制备单元; 将液体材料供给到制备单元的供给路径; 所述取出单元将所述测量样品从所述准备单元抽出到所述供给路径中，所述测量样品准备容纳经由所述供给路径供给到所述准备单元的液体材料; 以及测量单元，其测量由所述抽出单元抽出到所述供给路径中的所述测量样本的预定物理属性。

公开(公告)号：US08486788B2

公开(公告)日：2013-07-16

申请号：US13162310

申请日：2011-06-16

申请人： Junko Iwanaga ,  Takeshi Takagi ,  Yoshihiko Kanzawa ,  Haruyuki Sorada ,  Tohru Saitoh ,  Takahiro Kawashima

发明人： Junko Iwanaga ,  Takeshi Takagi ,  Yoshihiko Kanzawa ,  Haruyuki Sorada ,  Tohru Saitoh ,  Takahiro Kawashima

IPC分类号： H01L21/336

CPC分类号： H01L29/785 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/66795

摘要： A semiconductor device includes: a semiconductor substrate in which a trench is formed; a source region and a drain region each of which is buried in the trench and contains an impurity of the same conductive type; a semiconductor FIN buried in the trench and provided between the source and drain regions; a gate insulating film provided on a side surface of the semiconductor FIN as well as the upper surface of the semiconductor FIN; and a gate electrode formed on the gate insulating film.

摘要翻译： 一种半导体器件包括：形成沟槽的半导体衬底; 源极区域和漏极区域，每个源极区域和漏极区域被埋在沟槽中并且包含相同导电类型的杂质; 掩埋在沟槽中并设置在源区和漏区之间的半导体FIN; 设置在半导体FIN的侧表面上的栅极绝缘膜以及半导体FIN的上表面; 以及形成在栅极绝缘膜上的栅电极。