公开(公告)号：US09299568B2

公开(公告)日：2016-03-29

申请号：US13539461

申请日：2012-07-01

Applicant: Fredrick Jenne ,  Sagy Levy ,  Krishnaswamy Ramkumar

Inventor： Fredrick Jenne ,  Sagy Levy ,  Krishnaswamy Ramkumar

IPC: H01L21/336 ,  H01L21/28 ,  H01L21/314 ,  H01L29/51 ,  H01L29/792 ,  H01L29/66

CPC classification number: H01L29/792 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/02667 ,  H01L21/28282 ,  H01L21/3105 ,  H01L21/3143 ,  H01L29/04 ,  H01L29/16 ,  H01L29/42364 ,  H01L29/4916 ,  H01L29/513 ,  H01L29/515 ,  H01L29/518 ,  H01L29/66833

Abstract: A method of scaling a nonvolatile trapped-charge memory device and the device made thereby is provided. In an embodiment, the method includes forming a channel region including polysilicon electrically connecting a source region and a drain region in a substrate. A tunneling layer is formed on the substrate over the channel region by oxidizing the substrate to form an oxide film and nitridizing the oxide film. A multi-layer charge trapping layer including an oxygen-rich first layer and an oxygen-lean second layer is formed on the tunneling layer, and a blocking layer deposited on the multi-layer charge trapping layer. In one embodiment, the method further includes a dilute wet oxidation to densify a deposited blocking oxide and to oxidize a portion of the oxygen-lean second layer.

Abstract translation: 提供了一种缩放非易失性俘获电荷存储器件及其制造的器件的方法。 在一个实施例中，该方法包括形成包括电连接衬底中的源极区域和漏极区域的多晶硅沟道区域。 通过氧化衬底以在沟道区域上的衬底上形成隧穿层以形成氧化膜并氮化氧化膜。 在隧道层上形成包含富氧的第一层和无氧的第二层的多层电荷俘获层，以及沉积在多层电荷俘获层上的阻挡层。 在一个实施方案中，该方法还包括稀释的湿氧化以致密集沉积的阻塞氧化物并氧化贫氧的第二层的一部分。

公开(公告)号：US09023707B1

公开(公告)日：2015-05-05

申请号：US13312964

申请日：2011-12-06

Applicant: Krishnaswamy Ramkumar ,  Bo Jin ,  Fredrick B. Jenne

Inventor： Krishnaswamy Ramkumar ,  Bo Jin ,  Fredrick B. Jenne

IPC: H01L21/336 ,  H01L21/768

CPC classification number: H01L21/768 ,  H01L27/11568 ,  H01L29/792

Abstract: Methods of ONO integration into MOS flow are provided. In one embodiment, the method comprises: (i) forming a pad dielectric layer above a MOS device region of a substrate; and (ii) forming a patterned dielectric stack above a non-volatile device region of the substrate, the patterned dielectric stack comprising a tunnel layer, a charge-trapping layer, and a sacrificial top layer, the charge-trapping layer comprising multiple layers including a first nitride layer formed on the tunnel layer and a second nitride layer, wherein the first nitride layer is oxygen rich relative to the second nitride layer. Other embodiments are also described.

Abstract translation: 提供了ONO集成到MOS流中的方法。 在一个实施例中，该方法包括：（i）在衬底的MOS器件区域的上方形成焊盘电介质层; 并且（ii）在衬底的非易失性器件区域之上形成图案化的电介质堆叠，所述图案化的电介质叠层包括隧道层，电荷俘获层和牺牲顶层，所述电荷俘获层包括多个层，包括 形成在隧道层上的第一氮化物层和第二氮化物层，其中第一氮化物层相对于第二氮化物层富氧。 还描述了其它实施例。

公开(公告)号：US08822349B1

公开(公告)日：2014-09-02

申请号：US13401712

申请日：2012-02-21

Applicant: Jeong Soo Byun ,  Krishnaswamy Ramkumar

Inventor： Jeong Soo Byun ,  Krishnaswamy Ramkumar

IPC: H01L21/31

CPC classification number: H01L21/28282 ,  H01L21/02164 ,  H01L21/02238 ,  H01L21/02323 ,  H01L21/02326

Abstract: A method of making a semiconductor structure is provided. The method includes forming a dielectric layer using a high density plasma oxidation process. The dielectric layer is on a storage layer and the thickness of the storage layer is reduced during the high density plasma oxidation process.

Abstract translation: 提供制造半导体结构的方法。 该方法包括使用高密度等离子体氧化工艺形成介电层。 电介质层在存储层上，并且在高密度等离子体氧化过程中存储层的厚度减小。

公开(公告)号：US08685813B2

公开(公告)日：2014-04-01

申请号：US13428201

申请日：2012-03-23

Applicant: Krishnaswamy Ramkumar

Inventor： Krishnaswamy Ramkumar

IPC: H01L21/8238

CPC classification number: H01L27/11573 ,  H01L21/28282 ,  H01L21/823462 ,  H01L27/11565 ,  H01L27/11568 ,  H01L29/4916 ,  H01L29/495 ,  H01L29/792

Abstract: Embodiments of a method of integration of a non-volatile memory device into a MOS flow are described. Generally, the method includes: forming a dielectric stack on a surface of a substrate, the dielectric stack including a tunneling dielectric overlying the surface of the substrate and a charge-trapping layer overlying the tunneling dielectric; forming a cap layer overlying the dielectric stack; patterning the cap layer and the dielectric stack to form a gate stack of a memory device in a first region of the substrate and to remove the cap layer and the charge-trapping layer from a second region of the substrate; and performing an oxidation process to form a gate oxide of a MOS device overlying the surface of the substrate in the second region while simultaneously oxidizing the cap layer to form a blocking oxide overlying the charge-trapping layer. Other embodiments are also disclosed.

Abstract translation: 描述了将非易失性存储器件集成到MOS流中的方法的实施例。 通常，所述方法包括：在衬底的表面上形成电介质叠层，所述电介质堆叠包括覆盖所述衬底表面的隧道电介质和覆盖所述隧道电介质的电荷捕获层; 形成覆盖在所述电介质叠层上的盖层; 图案化所述盖层和所述电介质堆叠以在所述衬底的第一区域中形成存储器件的栅极叠层，并且从所述衬底的第二区域去除所述覆盖层和所述电荷俘获层; 以及进行氧化处理，以形成覆盖在第二区域中的衬底的表面上的MOS器件的栅极氧化物，同时对盖层进行氧化以形成覆盖电荷俘获层的阻挡氧化物。 还公开了其他实施例。

公开(公告)号：US08633537B2

公开(公告)日：2014-01-21

申请号：US13539466

申请日：2012-07-01

Applicant: Igor Polishchuk ,  Sagy Levy ,  Krishnaswamy Ramkumar

Inventor： Igor Polishchuk ,  Sagy Levy ,  Krishnaswamy Ramkumar

IPC: H01L29/792

CPC classification number: H01L29/4234 ,  B82Y10/00 ,  G11C16/0466 ,  H01L21/0214 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/28282 ,  H01L27/11526 ,  H01L27/11563 ,  H01L27/11568 ,  H01L27/11573 ,  H01L27/11575 ,  H01L29/0649 ,  H01L29/0676 ,  H01L29/42344 ,  H01L29/4916 ,  H01L29/511 ,  H01L29/512 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66795 ,  H01L29/66833 ,  H01L29/792 ,  H01L29/7926

Abstract: A semiconductor devices including non-volatile memories and methods of fabricating the same to improve performance thereof are provided. Generally, the device includes a memory transistor comprising a polysilicon channel region electrically connecting a source region and a drain region formed in a substrate, an oxide-nitride-nitride-oxide (ONNO) stack disposed above the channel region, and a high work function gate electrode formed over a surface of the ONNO stack. In one embodiment the ONNO stack includes a multi-layer charge-trapping region including an oxygen-rich first nitride layer and an oxygen-lean second nitride layer disposed above the first nitride layer. Other embodiments are also disclosed.

Abstract translation: 提供了包括非易失性存储器的半导体器件及其制造方法以提高其性能。 通常，器件包括存储晶体管，其包括电连接形成在衬底中的源极区域和漏极区域的多晶硅沟道区域，设置在沟道区域上方的氧化物氮化物 - 氮化物氧化物（ONNO）堆叠以及高功函数 栅电极形成在ONNO堆的表面上。 在一个实施方案中，ONNO堆叠包括多层电荷捕获区域，其包括富含氧的第一氮化物层和设置在第一氮化物层上方的无氧的第二氮化物层。 还公开了其他实施例。

公开(公告)号：US20130175604A1

公开(公告)日：2013-07-11

申请号：US13436875

申请日：2012-03-31

Applicant: Igor Polishchuk ,  Sagy Levy ,  Krishnaswamy Ramkumar

Inventor： Igor Polishchuk ,  Sagy Levy ,  Krishnaswamy Ramkumar

IPC: H01L29/792

CPC classification number: H01L29/7923 ,  B82Y10/00 ,  H01L21/28282 ,  H01L27/11578 ,  H01L29/0676 ,  H01L29/42392 ,  H01L29/4908 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66666 ,  H01L29/66742 ,  H01L29/66833 ,  H01L29/78642 ,  H01L29/78696 ,  H01L29/792 ,  H01L29/7926

Abstract: An embodiment of a nonvolatile charge trap memory device is described. In one embodiment, the device comprises a channel comprising silicon overlying a surface on a substrate electrically connecting a first diffusion region and a second diffusion region of the memory device, and a gate stack intersecting and overlying at least a portion of the channel, the gate stack comprising a tunnel oxide abutting the channel, a split charge-trapping region abutting the tunnel oxide, and a multi-layer blocking dielectric abutting the split charge-trapping region. The split charge-trapping region includes a first charge-trapping layer comprising a nitride closer to the tunnel oxide, and a second charge-trapping layer comprising a nitride overlying the first charge-trapping layer. The multi-layer blocking dielectric comprises at least a high-K dielectric layer.

Abstract translation: 描述了非易失性电荷陷阱存储器件的实施例。 在一个实施例中，该装置包括一个通道，该沟道包括覆盖在电连接存储器件的第一扩散区和第二扩散区的衬底上的表面的硅以及与沟道的至少一部分相交并且覆盖的栅极堆，栅极 包括邻接通道的隧道氧化物的堆叠，邻接隧道氧化物的分裂电荷捕获区域和与分离的电荷捕获区域邻接的多层阻挡电介质。 分离电荷捕获区域包括第一电荷捕获层，其包含更接近隧道氧化物的氮化物，以及包含覆盖在第一电荷俘获层上的氮化物的第二电荷俘获层。 多层阻挡电介质至少包括高K电介质层。

公开(公告)号：US08063434B1

公开(公告)日：2011-11-22

申请号：US12152518

申请日：2008-05-13

Applicant: Igor Polishchuk ,  Sagy Levy ,  Krishnaswamy Ramkumar

Inventor： Igor Polishchuk ,  Sagy Levy ,  Krishnaswamy Ramkumar

IPC: H01L29/792

CPC classification number: H01L29/513 ,  G11C16/0466 ,  G11C16/349 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/022 ,  H01L21/02271 ,  H01L21/28035 ,  H01L21/28282 ,  H01L27/11573 ,  H01L29/4234 ,  H01L29/4916 ,  H01L29/518 ,  H01L29/66833 ,  H01L29/792

Abstract: An embodiment of a semiconductor device includes a non-volatile memory transistor including an oxide-nitride-oxide (ONO) dielectric stack on a surface of a semiconductor substrate, the ONO dielectric stack comprising a multilayer charge storage layer including a silicon-rich, oxygen-lean top silicon oxynitride layer and a silicon-rich, oxygen-rich bottom silicon oxynitride layer, and a metal oxide semiconductor (MOS) logic transistor including a gate oxide and a high work function gate electrode.

Abstract translation: 半导体器件的实施例包括在半导体衬底的表面上包括氧化物 - 氧化物 - 氧化物（ONO）电介质堆叠的非易失性存储晶体管，所述ONO电介质堆叠包括多层电荷存储层，其包含富含硅的氧 - 富硅顶氧氮化硅层和富含硅的富氧底氧氮化硅层，以及包括栅极氧化物和高功函电极电极的金属氧化物半导体（MOS）逻辑晶体管。

公开(公告)号：US20110248332A1

公开(公告)日：2011-10-13

申请号：US13007533

申请日：2011-01-14

Applicant: Sagy Levy ,  Krishnaswamy Ramkumar ,  Fredrick Jenne ,  Sam Geha

Inventor： Sagy Levy ,  Krishnaswamy Ramkumar ,  Fredrick Jenne ,  Sam Geha

IPC: H01L29/792 ,  H01L21/3205

CPC classification number: H01L29/512 ,  C23C16/0272 ,  C23C16/308 ,  G11C16/0466 ,  H01L21/0214 ,  H01L21/02271 ,  H01L21/28282 ,  H01L21/3145 ,  H01L29/518 ,  H01L29/66833 ,  H01L29/7833 ,  H01L29/792

Abstract: A semiconductor device including a silicon-oxide-oxynitride-oxide-silicon structure and methods of forming the same are provided. Generally, the structure comprises: a tunnel oxide layer on a surface of a substrate including silicon; a multi-layer charge storing layer including an oxygen-rich, first oxynitride layer on the tunnel oxide layer in which the stoichiometric composition of the first oxynitride layer results in it being substantially trap free, and an oxygen-lean, second oxynitride layer on the first oxynitride layer in which the stoichiometric composition of the second oxynitride layer results in it being trap dense; a blocking oxide layer on the second oxynitride layer; and a silicon containing gate layer on the blocking oxide layer. Other embodiments are also disclosed.

Abstract translation: 提供了包括氧化硅 - 氧氮化物 - 氧化物 - 硅结构的半导体器件及其形成方法。 通常，该结构包括：在包括硅的衬底的表面上的隧道氧化物层; 多层电荷存储层，其包括在所述隧道氧化物层上的富氧第一氧氮化物层，其中所述第一氧氮化物层的化学计量组成导致其基本上不含杂质，并且所述第二氮氧化物层上的贫氧的第二氧氮化物层 第一氮氧化物层，其中第二氮氧化物层的化学计量组成导致其陷阱致密; 在第二氮氧化物层上的阻挡氧化物层; 以及在所述阻挡氧化物层上的含硅栅极层。 还公开了其他实施例。

公开(公告)号：US20080296661A1

公开(公告)日：2008-12-04

申请号：US12185747

申请日：2008-08-04

Applicant: Krishnaswamy Ramkumar ,  Ravindra Kapre ,  Jeremy Warren

Inventor： Krishnaswamy Ramkumar ,  Ravindra Kapre ,  Jeremy Warren

IPC: H01L29/792 ,  H01L21/336

CPC classification number: H01L29/7833 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823462 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7836 ,  H01L29/7843

Abstract: A semiconductor structure and method to form the same. The semiconductor structure includes a substrate having a non-volatile charge trap memory device disposed on a first region and a logic device disposed on a second region. A charge trap dielectric stack may be formed subsequent to forming wells and channels of the logic device. HF pre-cleans and SC1 cleans may be avoided to improve the quality of a blocking layer of the non-volatile charge trap memory device. The blocking layer may be thermally reoxidized or nitridized during a thermal oxidation or nitridation of a logic MOS gate insulator layer to densify the blocking layer. A multi-layered liner may be utilized to first offset a source and drain implant in a high voltage logic device and also block silicidation of the nonvolatile charge trap memory device.

公开(公告)号：US20070184597A1

公开(公告)日：2007-08-09

申请号：US11350160

申请日：2006-02-07

Applicant: Igor Polishchuk ,  Krishnaswamy Ramkumar ,  Sagy Levy

Inventor： Igor Polishchuk ,  Krishnaswamy Ramkumar ,  Sagy Levy

IPC: H01L21/8234

CPC classification number: H01L21/823807 ,  H01L21/823864 ,  H01L29/7843

Abstract: In one embodiment, a self-aligned contact (SAC) trench structure is formed through a dielectric layer to expose an active region of a MOS transistor. The SAC trench structure not only exposes the active region for electrical connection but also removes portions of a stress liner over the active region. This leaves the stress liner mostly on the sidewall and top of the gate of the MOS transistor. Removing portions of the stress liner over the active region substantially removes the lateral component of the strain imparted by the stress liner on the substrate, allowing for improved drive current without substantially degrading a complementary MOS transistor.

Abstract translation: 在一个实施例中，通过电介质层形成自对准接触（SAC）沟槽结构以暴露MOS晶体管的有源区。 SAC沟槽结构不仅暴露用于电连接的有源区，而且还去除了有源区上的应力衬垫的部分。 这使得应力衬垫主要在MOS晶体管的侧壁和顶部上方。 在有源区上去除应力衬垫的部分基本上消除了由衬底上的应力衬垫施加的应变的横向分量，从而允许改进的驱动电流而不会使互补MOS晶体管基本上降级。