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    Data-dependent equalizer circuit
    31.
    发明授权
    Data-dependent equalizer circuit 有权
    数据相关均衡电路

    公开(公告)号：US09252989B2

    公开(公告)日：2016-02-02

    申请号：US13628513

    申请日：2012-09-27

    Applicant: LSI Corporation

    Inventor： Jin Lu ,  Shaohua Yang ,  Weijun Tan

    IPC: H03D1/00 ,  H04L25/03

    CPC classification number: H04L25/03038

    Abstract: A data dependent equalizer circuit includes a plurality of noise prediction filters. Respective ones of the noise prediction filters are configured to filter noise in sample data for at least one predetermined non-return to zero (NRZ) condition. A plurality of equalizers is communicatively coupled with the plurality of noise prediction filters. Respective ones of the plurality of equalizers are configured to yield equalized sample data that corresponds to the at least one predetermined NRZ condition for one or more of the noise prediction filters.

    Abstract translation: 数据相关均衡器电路包括多个噪声预测滤波器。 各个噪声预测滤波器被配置为在至少一个预定的不归零（NRZ）条件下滤波采样数据中的噪声。 多个均衡器与多个噪声预测滤波器通信耦合。 多个均衡器中的各个均衡器被配置为产生对应于一个或多个噪声预测滤波器的至少一个预定NRZ条件的均衡样本数据。

    Multi-level enumerative encoder and decoder
    32.
    发明授权
    Multi-level enumerative encoder and decoder 有权
    多级枚举编码器和解码器

    公开(公告)号：US09251845B2

    公开(公告)日：2016-02-02

    申请号：US14318665

    申请日：2014-06-29

    Applicant: LSI Corporation

    Inventor： Victor Krachkovsky ,  Razmik Karabed ,  Shaohua Yang ,  Wu Chang

    IPC: G11B5/02 ,  G11B20/12

    CPC classification number: G11B20/1217 ,  G11B20/1833 ,  H03M7/4006 ,  H03M13/1102

    Abstract: A storage system includes a storage medium operable to maintain a data set, a read/write head assembly operable to write the data set to the storage medium and to read the data set from the storage medium, a multi-level enumerative encoder operable to encode the data set before it is written to the storage medium as encoded data, wherein the enumerative encoder applies an enumeration using a plurality of level-dependent bases, and a decoder operable to decode the data set after it is read from the storage medium.

    Abstract translation: 存储系统包括可操作以保持数据集的存储介质，可操作以将数据集写入存储介质并从存储介质读取数据集的读/写头组件，可操作以编码的多级枚举编码器 其前的数据集作为编码数据被写入存储介质，其中该枚举编码器使用多个依赖于水平的基站来应用枚举，以及解码器，用于在从存储介质读取数据集之后对其进行解码。

    LEH memory module architecture design in the multi-level LDPC coded iterative system
    34.
    发明授权
    LEH memory module architecture design in the multi-level LDPC coded iterative system 有权
    LEH存储器模块架构设计在多级LDPC编码迭代系统中

    公开(公告)号：US09219504B2

    公开(公告)日：2015-12-22

    申请号：US13663006

    申请日：2012-10-29

    Applicant: LSI Corporation

    Inventor： Zongwang Li ,  Lei Chen ,  Shaohua Yang ,  Johnson Yen

    IPC: H03M13/00 ,  H03M13/27 ,  H03M13/11

    CPC classification number: H03M13/6505 ,  H03M13/1111 ,  H03M13/1137 ,  H03M13/27 ,  H03M13/6331

    Abstract: A memory in a LDPC decoding system includes data banks organized into a ping-pong memory. The ping-pong memory is connected to an interleaver and a de-interleaver. The interleaver interleaves L values; the interleaved L values are then stored in the ping-pong memory. A LDPC decoder retrieves L values from the ping-pong memory and returns E values to the ping-pong memory. The de-interleaver de-interleaves the E values and sends data to a LE queue and HD queue.

    Abstract translation: LDPC解码系统中的存储器包括组织成乒乓存储器的数据库。 乒乓存储器连接到交织器和解交织器。 交织器交织L值; 然后将交错的L值存储在乒乓存储器中。 LDPC解码器从乒乓存储器检索L值并将E值返回给乒乓存储器。 解交织器对E值进行解交织，并将数据发送到LE队列和HD队列。

    System and Method for Elastic Despreader Memory Management
    35.
    发明申请
    System and Method for Elastic Despreader Memory Management 审中-公开
    弹性解扩器内存管理系统与方法

    公开(公告)号：US20150269097A1

    公开(公告)日：2015-09-24

    申请号：US14230908

    申请日：2014-03-31

    Applicant: LSI Corporation

    Inventor： Ku Hong Jeong ,  Qi Zuo ,  Shaohua Yang ,  Kaitlyn T. Nguyen

    IPC: G06F13/16

    CPC classification number: G06F13/1673 ,  G06F5/12 ,  G06F5/14 ,  H04L49/9005 ,  H04L49/9031 ,  H04L49/9036

    Abstract: The disclosure is directed to a system and method of managing memory resources in a communication channel. According to various embodiments, incoming memory slices associated with a plurality of data sectors are de-interleaved and transferred sequentially through a buffer to a decoder for further processing. To prevent buffer overflow or degraded decoder performance, the memory availability of the buffer is monitored, and transfers are suspended when the memory availability of the buffer is below a threshold buffer availability.

    Abstract translation: 本公开涉及一种管理通信信道中的存储器资源的系统和方法。 根据各种实施例，与多个数据扇区相关联的输入存储器片段被解交织并且顺序地通过缓冲器传送到解码器用于进一步处理。 为了防止缓冲区溢出或解码器性能下降，缓冲区的内存可用性受到监控，当缓冲区的内存可用性低于阈值缓冲区可用性时，传输将被暂停。

    Systems and methods for modified quality based priority scheduling during iterative data processing
    37.
    发明授权
    Systems and methods for modified quality based priority scheduling during iterative data processing 有权
    在迭代数据处理过程中改进质量优先级调度的系统和方法

    公开(公告)号：US09092368B2

    公开(公告)日：2015-07-28

    申请号：US13644589

    申请日：2012-10-04

    Applicant: LSI Corporation

    Inventor： Shaohua Yang ,  Fan Zhang ,  Jun Xiao

    IPC: G06F11/00 ,  G06F11/14 ,  G06F11/07 ,  G06F11/10

    CPC classification number: G06F11/14 ,  G06F11/0727 ,  G06F11/1004 ,  G11B20/10268

    Abstract: Systems, circuits, devices and/or methods related to systems and methods for data processing, and more particularly to systems and methods for priority based data processing. As one example, a data processing system is disclosed that includes a data detector circuit, a data decoder circuit, a memory circuit, and a scheduling circuit. The scheduling circuit is operable to select one of a first data set and the second data set as a detector input for processing by the data detector circuit.

    Abstract translation: 与用于数据处理的系统和方法相关的系统，电路，设备和/或方法，更具体地涉及用于基于优先级的数据处理的系统和方法。 作为一个示例，公开了一种数据处理系统，其包括数据检测器电路，数据解码器电路，存储器电路和调度电路。 调度电路可操作以选择第一数据组和第二数据组中的一个作为检测器输入进行数据检测器电路的处理。

    Majority-tabular post processing of quasi-cyclic low-density parity-check codes
    40.
    发明授权
    Majority-tabular post processing of quasi-cyclic low-density parity-check codes 有权
    准循环低密度奇偶校验码的大多数表格后处理

    公开(公告)号：US08977939B2

    公开(公告)日：2015-03-10

    申请号：US13723357

    申请日：2012-12-21

    Applicant: LSI Corporation

    Inventor： Alexander S. Podkolzin ,  Shaohua Yang ,  Lav D. Ivanovic ,  Sergey Afonin

    IPC: H03M13/00 ,  H03M13/11

    CPC classification number: H03M13/1142

    Abstract: A method for finding a valid codeword based on a near codeword trapping in a low-density parity-check decoding process includes identifying trapping set configurations and applying corrections to produce trapping sets with a limited number of invalid checks. Trapping set configurations are corrected in order to produce a trapping set in a table of trapping sets, the table associating each corrected trapping set with a valid codeword.

    Abstract translation: 基于在低密度奇偶校验解码过程中捕获的近码字来找到有效码字的方法包括识别陷印集合配置和应用校正以产生具有有限数量的无效检查的陷印集合。 修正陷阱集合配置以便在陷阱集合表中产生陷阱集合，该表将每个校正的捕获集合与有效码字相关联。

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