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37 条记录 (耗时 0.023 秒)

    Method and device for producing parts having a sealing layer on the surface, and corresponding parts
    31.
    发明授权
    Method and device for producing parts having a sealing layer on the surface, and corresponding parts 有权
    用于制造表面上具有密封层的部件的方法和装置以及相应的部件

    公开(公告)号：US07939137B2

    公开(公告)日：2011-05-10

    申请号：US10478143

    申请日：2002-05-16

    申请人： Klaus Becker-Weimann ,  Oliver Büker ,  Uwe Schroeder

    发明人： Klaus Becker-Weimann ,  Oliver Büker ,  Uwe Schroeder

    IPC分类号： B05D3/02

    CPC分类号： B05D5/00 ,  B05D1/265 ,  B05D1/28 ,  B05D7/08 ,  B05D2503/00

    摘要： The invention relates to a method and a device for producing parts (1) having a sealing layer (2) on the surface, and corresponding parts. Said method and device are improved in that the sealing layer (2) is applied to the surface in the form of a water-free and solvent-free reactive hot melt layer based on polyurethane and hardened by atmospheric humidity, and the inventive device comprises an application station (6), a transport device (5) and a smoothing station (8).

    摘要翻译： 本发明涉及一种用于制造在表面上具有密封层（2）的部件（1）和相应部件的方法和装置。 所述方法和装置的改进在于，密封层（2）以基于聚氨酯的无水和无溶剂的反应性热熔体层的形式施加到表面，并且由大气湿度硬化，并且本发明的装置包括 应用站（6），传送设备（5）和平滑站（8）。

    Method for fabricating an electrical component
    32.
    发明申请
    Method for fabricating an electrical component 有权
    电气部件的制造方法

    公开(公告)号：US20060234463A1

    公开(公告)日：2006-10-19

    申请号：US11399811

    申请日：2006-04-07

    申请人： Alejandro Avellan ,  Thomas Hecht ,  Stefan Jakschik ,  Uwe Schroeder

    发明人： Alejandro Avellan ,  Thomas Hecht ,  Stefan Jakschik ,  Uwe Schroeder

    IPC分类号： H01L21/20 ,  H01L21/8242 ,  H01L21/31 ,  H01L21/469

    CPC分类号： H01L28/65 ,  H01L27/1087 ,  H01L29/66181

    摘要： An electrical component, such as a DRAM semiconductor memory or a field-effect transistor is fabricated. At least one capacitor having a dielectric (130) and at least one connection electrode (120, 140) are fabricated. To enable the capacitors fabricated to have optimum storage properties even for very small capacitor structures, the dielectric (130) or the connection electrode (120, 140) are formed in such a manner that transient polarization effects are prevented or at least reduced.

    摘要翻译： 制造诸如DRAM半导体存储器或场效应晶体管的电气部件。 制造具有电介质（130）和至少一个连接电极（120,140）的至少一个电容器。 为了使得制造的电容器即使对于非常小的电容器结构也具有最佳的存储特性，电介质（130）或连接电极（120,140）形成为使得瞬态极化效应被防止或至少减小。

    Method of forming isolated features of semiconductor devices
    33.
    发明申请
    Method of forming isolated features of semiconductor devices 有权
    形成半导体器件隔离特征的方法

    公开(公告)号：US20060189122A1

    公开(公告)日：2006-08-24

    申请号：US11062722

    申请日：2005-02-22

    申请人： Uwe Schroeder

    发明人： Uwe Schroeder

    IPC分类号： H01L21/4763

    CPC分类号： H01L21/0337 ,  H01L21/0332 ,  H01L21/76816 ,  H01L21/76838

    摘要： A method of forming isolated features of semiconductor devices is disclosed. A first hard mask is deposited over a material layer to be patterned, and a second hard mask is deposited over the first hard mask. The second hard mask is patterned with a pattern for an array of features using an off-axis lithography method. A portion of the pattern for the array of features is transferred to the first hard mask. The first hard mask is then used as a mask to pattern the material layer.

    摘要翻译： 公开了形成半导体器件的隔离特征的方法。 将第一硬掩模沉积在待图案化的材料层上，并且第二硬掩模沉积在第一硬掩模上。 使用离轴光刻方法，第二硬掩模用特征阵列图案化。 特征阵列的图案的一部分被转移到第一硬掩模。 然后将第一个硬掩模用作掩模以图案化材料层。

    Method for exposing a substrate with a structure pattern which compensates for the optical proximity effect
    34.
    发明申请
    Method for exposing a substrate with a structure pattern which compensates for the optical proximity effect 有权
    用补偿光学邻近效应的结构图案曝光衬底的方法

    公开(公告)号：US20060024594A1

    公开(公告)日：2006-02-02

    申请号：US10771302

    申请日：2004-02-05

    申请人： Uwe Schroeder

    发明人： Uwe Schroeder

    IPC分类号： G03C5/00 ,  G03F1/00 ,  G06F17/50

    CPC分类号： G03F7/70441 ,  G03F1/36

    摘要： In a circuit layout, a partial area is defined in a first structure pattern, which is stored electronically in a data format and represents a first lithographic plane, in which partial area a lower limit value for the length of a serif to be added to a structure element in an OPC correction can be undershot in order to locally increase the resolution. The partial area in the electronically stored circuit layout maybe, for example, an active region with which contact is to be made and which has been selected in a second structure pattern of a further lithographic plane as a structure element. Thus, within such a partial area of an integrated circuit, elevated requirements made of dimensionally accurate imaging are satisfied, while the required data volume overall increases only to an insignificant extent.

    摘要翻译： 在电路布局中，部分区域以第一结构图形定义，其以电子方式存储在数据格式中并且表示第一光刻平面，其中部分区域是要添加到衬底的衬线的长度的下限值 OPC校正中的结构元素可能不足以局部地提高分辨率。 电子存储电路布局中的部分区域可以是例如要与其形成接触的有源区域，并且已经以另一光刻平面的第二结构图案作为结构元件选择。 因此，在集成电路的这样的部分区域内，满足了对尺寸精确成像的高要求，而所需数据量总体上仅增加到不显着的程度。

    Modified gate processing for optimized definition of array and logic devices on same chip
    37.
    发明授权
    Modified gate processing for optimized definition of array and logic devices on same chip 失效
    改进的门处理，用于在同一芯片上优化阵列和逻辑器件的定义

    公开(公告)号：US06548357B2

    公开(公告)日：2003-04-15

    申请号：US10117869

    申请日：2002-04-08

    申请人： Mary E. Weybright ,  Gary Bronner ,  Richard A. Conti ,  Ramachandra Divakaruni ,  Jeffrey Peter Gambino ,  Peter Hoh ,  Uwe Schroeder

    发明人： Mary E. Weybright ,  Gary Bronner ,  Richard A. Conti ,  Ramachandra Divakaruni ,  Jeffrey Peter Gambino ,  Peter Hoh ,  Uwe Schroeder

    IPC分类号： H01L21336

    CPC分类号： H01L27/10894 ,  H01L21/76897 ,  H01L21/823456 ,  H01L27/1052 ,  H01L27/10873

    摘要： Two different gate conductor dielectric caps are used in the array and support device regions so that the bitline contact can be fabricated in the array region, but a thinner hard mask can be used for better linewidth control in the support device region. The thinner dielectric cap is made into dielectric spacers in the array device regions during support mask etching. These dielectric spacers allow for the array gate conductor resist line to be made smaller than the final gate conductor linewidth. This widens the array gate conductor processing window. The second dielectric cap layer improves linewidth control for the support devices and the array devices. Two separate gate conductor lithography steps and gate conductor dielectric etches are carried out in the present invention to optimize the gate conductor linewidth control in the array and support device regions. The gate conductors in the array and support devices regions are etched simultaneously to reduce production cost. In additional embodiments of the invention, dual workfunction support device transistors with or without salicide can be fabricated with an array including borderless contacts.

    摘要翻译： 在阵列和支撑器件区域中使用两个不同的栅极导体电介质盖，使得可以在阵列区域中制造位线接触，但是可以使用较薄的硬掩模用于支撑装置区域中的更好的线宽控制。 在支撑掩模蚀刻期间，将较薄的介质盖制成阵列器件区域中的电介质间隔物。 这些介质间隔物允许使阵列栅极导体抗蚀剂线小于最终的栅极导体线宽。 这扩大了阵列栅极导体处理窗口。 第二电介质盖层改善了支撑装置和阵列装置的线宽控制。 在本发明中执行两个单独的栅极导体光刻步骤和栅极导体介电蚀刻，以优化阵列和支撑装置区域中的栅极导体线宽控制。 阵列和支撑装置区域中的栅极导体被同时蚀刻以降低生产成本。 在本发明的另外的实施例中，可以用包括无边界触点的阵列来制造具有或不具有自对准硅的双功能功能支撑器件晶体管。