公开(公告)号：US09536887B2

公开(公告)日：2017-01-03

申请号：US14519906

申请日：2014-10-21

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Yu-Fong Huang ,  Kun-Mou Chan ,  Tzung-Ting Han

IPC: H01L21/70 ,  H01L29/788 ,  H01L23/48 ,  H01L27/115 ,  H01L21/764 ,  H01L21/768

CPC classification number: H01L27/11521 ,  H01L21/764 ,  H01L21/7682 ,  H01L27/11524 ,  H01L27/11568

Abstract: A process for fabricating a gate structure, the gate structure having a plurality of gates defined by a network of spaces. The word line (WL) spaces within a dense WL region having airgaps and those spaces outside of the dense WL being substantially free of airgaps. A gate structure having a silicide layer dispose across the plurality of gates is also provided.

Abstract translation: 一种用于制造栅极结构的工艺，所述栅极结构具有由空间网络限定的多个栅极。 具有气隙的密集WL区域内的字线（WL）空间，密集WL外部的那些空间基本上没有空气隙。 还提供了具有跨越多个栅极的硅化物层的栅极结构。

公开(公告)号：US20160020216A1

公开(公告)日：2016-01-21

申请号：US14333893

申请日：2014-07-17

Applicant: Macronix International Co., Ltd.

Inventor： Shang-Wei Lin ,  Yu-Wei Hsu ,  Yu-Min Hung ,  Tzung-Ting Han

IPC: H01L27/115 ,  H01L21/28

CPC classification number: H01L27/11521 ,  H01L29/40114 ,  H01L29/42324 ,  H01L29/66825

Abstract: A memory device is provided having a plurality of floating gates and control gates, which at least one control gate has been removed after applying a flowable material to the semiconductor which prevents damage to the substrate when the control gate is removed. Methods of manufacturing such a memory device are also provided.

Abstract translation: 提供具有多个浮动栅极和控制栅极的存储器件，在将可流动材料施加到半导体之后，至少一个控制栅极被去除，这防止了在控制栅极被去除时损坏衬底。 还提供了制造这种存储器件的方法。

公开(公告)号：US12256548B2

公开(公告)日：2025-03-18

申请号：US17748121

申请日：2022-05-19

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Chen-Yu Cheng ,  Tzung-Ting Han

IPC: H01L27/11578 ,  H01L27/11565 ,  H10B43/10 ,  H10B43/20 ,  H10B43/27 ,  H10B43/40 ,  H10B43/50

Abstract: A semiconductor device includes a circuit board, a bottom plate, landing pads, a stack, support pillars, and memory pillars. The circuit board includes circuit structures and wires and has a peripheral area, an array area and a staircase area disposed between the peripheral area and the array area. The bottom plate is disposed on the circuit board, and the bottom plate includes a bottom conductive layer. The landing pads are embedded in at least a top portion of the bottom conductive layer and contact the bottom conductive layer in the staircase area. The stack is disposed on the bottom plate, and includes conductive layers and insulating layers alternately stacked along a first direction. The support pillars pass through the stack along the first direction and extend to the landing pads in the staircase area. The memory pillars pass through the stack along the first direction in the array area.

公开(公告)号：US20240414921A1

公开(公告)日：2024-12-12

申请号：US18331805

申请日：2023-06-08

Applicant: MACRONIX International Co., Ltd.

Inventor： Chen-Yu Cheng ,  Tzung-Ting Han

IPC: H10B43/35 ,  H01L23/522 ,  H01L23/528 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27

Abstract: A memory device includes a substrate, a composite stacked structure, multiple first insulating structures, and multiple through vias. The substrate includes a memory plane region and a periphery region. The composite stacked structure is located on the substrate in the memory plane region and the periphery region, wherein the composite stacked structure includes a first stacked structure. The first stacked structure includes multiple first insulating layers and multiple intermediate layers alternately stacked on each other, and is located on the substrate in the periphery region. The first insulating structures are separated from each other, extend through the first stacked structure in the periphery region, and are respectively surrounded by the first insulating layers and the intermediate layers. The through vias extend through one of the first insulating structures.

公开(公告)号：US12062615B2

公开(公告)日：2024-08-13

申请号：US18164626

申请日：2023-02-06

Applicant: MACRONIX International Co., Ltd.

Inventor： Ching Hung Wang ,  Shih Chin Lee ,  Chen-Yu Cheng ,  Tzung-Ting Han

IPC: H01L23/535 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H10B41/27 ,  H10B41/41 ,  H10B43/27 ,  H10B43/40

CPC classification number: H01L23/535 ,  H01L21/76805 ,  H01L21/76895 ,  H01L23/5226 ,  H01L23/5283 ,  H10B41/27 ,  H10B41/41 ,  H10B43/27 ,  H10B43/40

Abstract: Provided is a memory device including a substrate, a stack structure, a plurality of pads and an additional dielectric layer. The substrate has an array region and a staircase region. The stack structure is disposed on the substrate. The stack structure includes a plurality of dielectric layers and a plurality of conductive layers stacked alternately. The pads are disposed on the substrate in the staircase region. The pads are respectively connected to the conductive layers, so as to form a staircase structure. The additional dielectric layer is disposed on the stack structure to contact a topmost conductive layer of the conductive layers. A topmost pad of the pads includes a landing portion to contact a plug and an extension portion. The landing portion is laterally adjacent to the additional dielectric layer, and the extension portion extends over a top surface of the additional dielectric layer.

公开(公告)号：US20230120621A1

公开(公告)日：2023-04-20

申请号：US17505487

申请日：2021-10-19

Applicant: MACRONIX International Co., Ltd.

Inventor： Chih-Kai Yang ,  Tzung-Ting Han

IPC: H01L27/11582 ,  H01L23/535 ,  H01L27/11556 ,  H01L21/225 ,  H01L21/768

Abstract: An embodiment of the present the disclosure provides a memory device, including: a substrate, an interconnection structure disposed on the substrate, a conductive layer disposed on the interconnection structure, a stop layer disposed on the conductive layer, and a gate stack structure disposed on the stop layer. The gate stack structure includes a plurality of insulating layers and a plurality of gate conductive layers that alternate with each other. A ratio of a thickness of a bottommost insulating layer of the gate stack structure to a thickness of the stop layer is 1:1 to 1:2. The memory device further includes a channel pillar extending through the gate stack structure and the stop layer and to electrically connect the conductive layer, and a charge storage structure disposed between sidewalls of the channel pillar and the plurality of gate conductive layers.

公开(公告)号：US11515319B2

公开(公告)日：2022-11-29

申请号：US16867063

申请日：2020-05-05

Applicant: Macronix International Co., Ltd.

Inventor： Chen-Yu Cheng ,  Tzung-Ting Han

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L23/00 ,  H01L27/11556 ,  G11C5/02 ,  H01L27/06

Abstract: Methods and apparatus for fabricating memory devices are provided. In one aspect, an intermediate stack of dielectric layers are formed on a first stack of dielectric layers in a first tier. The intermediate stack of dielectric layers is then partially or fully etched and have a landing pad layer deposited thereon. In response to planarizing the landing pad layer to expose a top surface of the intermediate stack of dielectric layers, a second stack of dielectric layers are deposited above the planarized landing pad layer. A staircase is formed by etching through the second stack, the intermediate stack, and the first stack of dielectric layers in the staircase region of the memory device. The staircase is located adjacent to one end of the center landing pad, where steps of the staircase are formed within the thickness of the center landing pad.

公开(公告)号：US11411020B2

公开(公告)日：2022-08-09

申请号：US16855732

申请日：2020-04-22

Applicant: MACRONIX International Co., Ltd.

Inventor： Chih-Kai Yang ,  Tzung-Ting Han

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11519 ,  H01L21/768 ,  H01L23/522 ,  H01L23/00 ,  H01L27/1157

Abstract: Provided is a memory device including a substrate, a stack structure, a first set of vertical channel structures, a second set of vertical channel structures, and a first slit. The stack structure is disposed on the substrate. The first and second sets of vertical channel structures are arranged along a Y direction and penetrate through the stack structure to contact the substrate. The first slit is disposed between the first and second sets of vertical channel structures, and penetrates through the stack structure to expose the substrate. The first slit includes a plurality of first sub-slits discretely disposed along a X direction.

公开(公告)号：US20210335801A1

公开(公告)日：2021-10-28

申请号：US16855732

申请日：2020-04-22

Applicant: MACRONIX International Co., Ltd.

Inventor： Chih-Kai Yang ,  Tzung-Ting Han

IPC: H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/1157 ,  H01L27/11565 ,  H01L23/522 ,  H01L23/00 ,  H01L21/768

Abstract: Provided is a memory device including a substrate, a stack structure, a first set of vertical channel structures, a second set of vertical channel structures, and a first slit. The stack structure is disposed on the substrate. The first and second sets of vertical channel structures are arranged along a Y direction and penetrate through the stack structure to contact the substrate. The first slit is disposed between the first and second sets of vertical channel structures, and penetrates through the stack structure to expose the substrate. The first slit includes a plurality of first sub-slits discretely disposed along a X direction.

公开(公告)号：US20190198630A1

公开(公告)日：2019-06-27

申请号：US15849971

申请日：2017-12-21

Applicant: Macronix International Co., Ltd.

Inventor： Chien-Ying Lee ,  Chih-Hsiung Lee ,  Tzung-Ting Han

IPC: H01L29/423 ,  H01L21/28 ,  H01L21/3213 ,  H01L29/66 ,  H01L29/06 ,  H01L29/788 ,  H01L27/11521

CPC classification number: H01L29/42324 ,  H01L21/28273 ,  H01L21/32137 ,  H01L21/32139 ,  H01L27/11521 ,  H01L29/0649 ,  H01L29/42376 ,  H01L29/66825 ,  H01L29/7883

Abstract: Methods of managing gate coupling for semiconductor devices, e.g., non-volatile memory devices, are provided. The methods include: providing a conductive layer on a semiconductor substrate, the conductive layer including a lower conductive layer and an upper conductive layer, the lower conductive layer including a first material and the upper conductive layer including a second material having at least one property different from the first material, forming a protective pattern on the conductive layer, and etching through the conductive layer to obtain individual separated gates by controlling an etching process such that the first material has a higher etching rate than the second material during the etching process, each of the gates including an upper gate and a lower gate, the lower gate having a smaller width than the upper gate after the etching process.