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    MEMORY CELL SENSING USING A BOOST VOLTAGE
    32.
    发明申请
    MEMORY CELL SENSING USING A BOOST VOLTAGE 有权
    使用升压电压进行记忆细胞感测

    公开(公告)号：US20140177342A1

    公开(公告)日：2014-06-26

    申请号：US14132124

    申请日：2013-12-18

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Violante Moschiano ,  Domenico Di Cicco ,  Andrea D'Alessandro

    IPC: G11C16/26

    CPC classification number: G11C16/26 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/3436

    Abstract: The present disclosure includes devices, methods, and systems including memory cell sensing using a boost voltage. One or more embodiments include pre-charging and/or floating a data line associated with a selected memory cell, boosting the pre-charged and/or floating data line, and determining a state of the selected memory cell based on a sensed discharge of the data line after boosting the data line.

    Abstract translation: 本公开包括包括使用升压电压的存储器单元感测的装置，方法和系统。 一个或多个实施例包括预先充电和/或浮动与所选择的存储器单元相关联的数据线，升压预充电和/或浮置数据线，以及基于感测到的放电，确定所选择的存储器单元的状态 提升数据线后的数据线。

    BITLINE DRIVER ISOLATION FROM PAGE BUFFER CIRCUITRY IN MEMORY DEVICE
    35.
    发明申请
    BITLINE DRIVER ISOLATION FROM PAGE BUFFER CIRCUITRY IN MEMORY DEVICE 有权

    公开(公告)号：US20220180936A1

    公开(公告)日：2022-06-09

    申请号：US17678960

    申请日：2022-02-23

    Applicant: Micron Technology, Inc.

    Inventor： Violante Moschiano ,  Dheeraj Srinivasan ,  Andrea D'Alessandro

    IPC: G11C16/24 ,  G11C16/04 ,  G11C16/26

    Abstract: A page buffer circuit in a memory device includes a logic element configured to perform a series of calculations pertaining to one or more memory access operations and generate a plurality of calculation results associated with the series of calculations and a dynamic memory element coupled with the logic element and configured to store the plurality of calculation results. The page buffer circuit further includes an isolation element coupled between the logic element and the dynamic memory element, the isolation element to permit a calculation result from the logic element to pass to the dynamic memory element when activated and a circuit coupled to the dynamic memory element and configured to perform pre-charging operations associated with the one or more memory access operations and based at least in part on the plurality of calculation results stored in the dynamic memory element. The circuit coupled to the dynamic memory element can perform a first operation on the memory array based at least in part on a first calculation result stored in the dynamic memory element during a first period of time when the isolation element is deactivated to disconnect the logic element from the dynamic memory element, and the logic element is configured to concurrently generate a second calculation result during the first period of time.

    HYBRID ROUTINE FOR A MEMORY DEVICE
    36.
    发明申请
    HYBRID ROUTINE FOR A MEMORY DEVICE 有权

    公开(公告)号：US20220059173A1

    公开(公告)日：2022-02-24

    申请号：US16996363

    申请日：2020-08-18

    Applicant: Micron Technology, Inc.

    Inventor： Shannon Marissa Hansen ,  Fulvio Rori ,  Andrea D'Alessandro ,  Jason Lee Nevill ,  Chiara Cerafogli

    IPC: G11C16/20 ,  G11C16/04 ,  G11C16/24 ,  G11C16/26 ,  G06F3/06

    Abstract: A variety of applications can include a memory device designed to perform sensing of a memory cell of a string of memory cells using a modified shielded bit line sensing operation. The modified shielded bit line sensing operation includes pre-charging a data line corresponding to the string with the string enabled to couple to the data line. The modified shielded bit line sensing operation can be implemented in a hybrid initialization routine for the memory device. The hybrid initialization routine can include a sensing read routine corresponding to an all data line configuration of data lines of the memory device and a modified sensing read routine corresponding to a shielded data line configuration of the data lines with selected strings enabled during pre-charging. A read retry routine associated with the modified sensing read routine can be added to the hybrid initialization routine. Additional devices, systems, and methods are discussed.

    PRE-COMPENSATION OF MEMORY THRESHOLD VOLTAGE
    39.
    发明申请
    PRE-COMPENSATION OF MEMORY THRESHOLD VOLTAGE 审中-公开

    公开(公告)号：US20170345511A1

    公开(公告)日：2017-11-30

    申请号：US15449426

    申请日：2017-03-03

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Tommaso Vali ,  Andrea D'Alessandro ,  Violante Moschiano ,  Mattia Cichocki ,  Michele Incarnati ,  Federica Paolini

    IPC: G11C16/34 ,  G11C16/10 ,  G11C11/56 ,  G11C16/26 ,  G11C16/14

    CPC classification number: G11C16/3459 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26 ,  G11C16/3427 ,  G11C2211/5621 ,  G11C2211/5648

    Abstract: Methods of operating a memory include storing a first target data state of multiple possible data states of a first memory cell to be programmed in a target data latch coupled to a data node, storing at least one bit of a second target data state of the multiple possible data states of a second memory cell to be programmed in an aggressor data latch coupled to the data node, and programming the first memory cell and performing a program verify operation for the first target data state to determine if the first memory cell is verified for the first target data state. The program verify operation including: an intermediate verify corresponding to an amount of aggression to apply a voltage to the data node when performing the intermediate verify, based on the at least one bit of the second target state stored in the aggressor data latch; and a program verify corresponding to a condition of no aggression to apply to the voltage to the data node when performing the program verify, based on the at least one bit of the second target state stored in the aggressor data latch. The methods including inhibiting the first memory cell from further programming if the first memory cell is verified during the intermediate verify and the at least one bit in the aggressor data latch corresponds to the particular amount of aggression, or the first memory cell is verified during the program verify and the at least one bit in the aggressor data latch corresponds to the condition of no aggression. The second memory cell is a neighbor of the first memory cell.

    Methods and apparatus for sensing a memory cell
    40.
    发明授权
    Methods and apparatus for sensing a memory cell 有权
    用于感测存储器单元的方法和装置

    公开(公告)号：US09299449B2

    公开(公告)日：2016-03-29

    申请号：US14886536

    申请日：2015-10-19

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Andrea D'Alessandro ,  Violante Moschiano

    IPC: G11C7/10 ,  G11C16/26 ,  G11C16/24

    CPC classification number: G11C16/26 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/24

    Abstract: Methods of operating a memory include selectively discharging a data line through a memory cell selected for sensing, discharging a sense node to the data line while a voltage level of the sense node is greater than a voltage level of the data line, and inhibiting discharging of the data line to the sense node while the voltage level of the data line is greater than the voltage level of the sense node. Sense circuits include a path between an input node and a sense node facilitating current flow from the sense node to the input node when a voltage level of the sense node is greater than a voltage level of the input node and inhibiting current flow from the input node to the sense node when the voltage level of the sense node is less than the voltage level of the input node.

    Abstract translation: 操作存储器的方法包括：选择性地将数据线放电通过选择用于感测的感应节点到数据线的存储单元放电，同时感测节点的电压电平大于数据线的电压电平，并且抑制放电 数据线到数据线的电压电平大于感测节点的电压电平的数据线。 当检测节点的电压电平大于输入节点的电压电平并且阻止来自输入节点的电流流动时，检测电路包括输入节点和感测节点之间的路径，促进从感测节点到输入节点的电流流动 当感测节点的电压电平小于输入节点的电压电平时，到感测节点。

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