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    DEDICATED COMMANDS FOR MEMORY OPERATIONS
    32.
    发明申请
    DEDICATED COMMANDS FOR MEMORY OPERATIONS 有权

    公开(公告)号：US20210319829A1

    公开(公告)日：2021-10-14

    申请号：US16846481

    申请日：2020-04-13

    Applicant: Micron Technology, Inc.

    Inventor： Daniele Balluchi ,  Paolo Amato ,  Graziano Mirichigni ,  Danilo Caraccio ,  Marco Sforzin ,  Marco Dallabora

    IPC: G11C13/00

    Abstract: An apparatus can have a memory comprising an array of resistance variable memory cells and a controller. The controller can be configured to receive to a dedicated command to write all cells in a number of groups of the resistance variable memory cells to a first state without transferring any host data corresponding to the first state to the number of groups. The controller can be configured to, in response to the dedicated command, perform a read operation on each respective group to determine states of the cells in each respective group, determine from the read operation any cells in each respective group programmed to a second state, and write only the cells determined to be in the second state to the first state.

    BANK CONFIGURABLE POWER MODES
    33.
    发明申请
    BANK CONFIGURABLE POWER MODES 有权

    公开(公告)号：US20210064119A1

    公开(公告)日：2021-03-04

    申请号：US16551581

    申请日：2019-08-26

    Applicant: Micron Technology, Inc.

    Inventor： Graziano Mirichigni ,  Andrea Martinelli ,  Christophe Vincent Antoine Laurent

    IPC: G06F1/3287 ,  G06F1/3234 ,  G06F1/28 ,  G11C11/22 ,  G11C11/4096

    Abstract: Methods, systems, and devices for bank-configurable power modes are described. Aspects include operating a memory device that has multiple memory banks in a first mode. While operating in the first mode, the memory device may receive a command to enter a second mode having a lower power consumption level than the first mode. The memory device may enter the second mode by switching a first subset of the memory banks to a first low power mode that operates at a first power consumption level and a second subset of the memory banks to a second low power mode that operates at a second power consumption level that may be lower than the first power consumption level. In some cases, the memory device may switch the first subset of memory banks from the first low power mode while maintaining the second subset of memory banks in the low power mode.

    Transaction metadata
    35.
    发明授权
    Transaction metadata 有权

    公开(公告)号：US10733046B2

    公开(公告)日：2020-08-04

    申请号：US15958401

    申请日：2018-04-20

    Applicant: Micron Technology, Inc.

    Inventor： Graziano Mirichigni ,  Marco Sforzin ,  Paolo Amato ,  Danilo Caraccio

    IPC: H03M13/00 ,  G06F11/10 ,  G06F9/46 ,  G06F13/16

    Abstract: Apparatuses and methods related to providing transaction metadata. Providing transaction metadata includes providing an address of data stored in the memory device using an address bus coupled to the memory device and the controller. Providing transaction metadata also includes transferring the data, associated with the address, from the memory device using a data bus coupled to the memory device and the controller. Providing transaction metadata further includes transferring a sideband signal synchronously with the data bus and in conjunction with the address bus using a transaction metadata bus coupled to the memory device and the controller.

    AUTO-REFERENCED MEMORY CELL READ TECHNIQUES
    36.
    发明申请
    AUTO-REFERENCED MEMORY CELL READ TECHNIQUES 审中-公开

    公开(公告)号：US20200035297A1

    公开(公告)日：2020-01-30

    申请号：US16536120

    申请日：2019-08-08

    Applicant: Micron Technology, Inc.

    Inventor： Graziano Mirichigni ,  Paolo Amato ,  Federico Pio ,  Alessandro Orlando ,  Marco Sforzin

    IPC: G11C13/00 ,  G11C11/56 ,  H01L45/00 ,  H01L27/24

    Abstract: Methods, systems, and devices related to auto-referenced memory cell read techniques are described. The auto-referenced read may encode user data to include a predetermined number of bits having a first logic state prior to storing the user data in memory cells. The auto-referenced read may store a total number of bits of the user data having a first logic state in a separate set of memory cells. Subsequently, reading the user data may be carried out by applying a read voltage to the memory cells storing the user data while monitoring a series of switching events by activating a subset of the memory cells having the first logic state. During the read operation, the auto-referenced read may compare the number of activated memory cells to either the predetermined number or the total number to determine whether all the bits having the first logic state has been detected. When the number of activated memory cells matches either the predetermined number or the total number, the auto-referenced read may determine that the memory cells that have been activated correspond to the first logic state.

    STORAGE CLASS MEMORY STATUS
    37.
    发明申请
    STORAGE CLASS MEMORY STATUS 审中-公开

    公开(公告)号：US20190266078A1

    公开(公告)日：2019-08-29

    申请号：US15908545

    申请日：2018-02-28

    Applicant: Micron Technology, Inc.

    Inventor： Luca Porzio ,  Graziano Mirichigni ,  Danilo Caraccio

    IPC: G06F12/02 ,  G06F12/1009 ,  G06F3/06 ,  G11C29/52

    Abstract: Devices and techniques for storage class memory status are disclosed herein. A storage portion characteristics data structure is maintained. Here, the data structure includes an array of elements—where each element is sized to contain a reference to a storage portion in a storage class memory storage device, a first pointer to a first element in the array of elements, a second pointer to a second element in the array of elements, and a third pointer to a third element in the array of elements. The data structure includes a direction of pointer motion in which the second pointer precedes the third pointer and the first pointer precedes the second pointer with respect to the direction of pointer motion. A write request is performed to a storage portion reference retrieved from the first element. The first pointer is then advanced.

    AUTO-REFERENCED MEMORY CELL READ TECHNIQUES
    39.
    发明申请
    AUTO-REFERENCED MEMORY CELL READ TECHNIQUES 审中-公开

    公开(公告)号：US20190198096A1

    公开(公告)日：2019-06-27

    申请号：US15853328

    申请日：2017-12-22

    Applicant: Micron Technology, Inc.

    Inventor： Graziano Mirichigni ,  Marco Sforzin ,  Alessandro Orlando

    IPC: G11C11/56 ,  G11C16/32 ,  G11C16/08 ,  G11C16/30 ,  G11C8/14

    Abstract: Methods, systems, and devices related to auto-referenced memory cell read techniques are described. The auto-referenced read may encode user data to include a certain number bits having a first logic state prior to storing the user data in memory cells. Subsequently, reading the encoded user data may be carried out by applying a read voltage to the memory cells while monitoring a series of switching events by activating a subset of the memory cells having the first logic state. The auto-referenced read may identify a particular switching event that correlates to a median threshold voltage value of the subset of the memory cells. Then, the auto-referenced read may determine a reference voltage that takes into account a statistical property of threshold voltage distribution of the subset of the memory cells. The auto-referenced read may identify a time duration to maintain the read voltage based on determining the reference voltage. When the time duration expires, the auto-referenced read may determine that the memory cells that have been activated correspond to the first logic state.

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