公开(公告)号：US12072381B2

公开(公告)日：2024-08-27

申请号：US18047386

申请日：2022-10-18

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Kenneth M. Curewitz ,  Jaime Cummins ,  John D. Porter ,  Bryce D. Cook ,  Jeffrey P. Wright

IPC: G01R31/319 ,  G01R31/3185

CPC classification number: G01R31/31907 ,  G01R31/318594 ,  G01R31/318597

Abstract: A memory controller and a physical interface layer may accommodate multiple memory types. In some examples, the memory controller and/or PHY may include a register that includes operating parameters for multiple operating modes. Different operating modes may be compatible with different memory types. In some examples, the memory controller and physical interface may be included in a system for testing multiple memory types. The system may provide multiple interfaces for communicating with the memory. The different communication types may be used for performing different tests and/or simulating different types of devices that may utilize the memory.

公开(公告)号：US20230116534A1

公开(公告)日：2023-04-13

申请号：US17450582

申请日：2021-10-12

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Donald M. Morgan ,  Alan J. Wilson ,  Bryan D. Kerstetter ,  John D. Porter

IPC: G11C29/00

Abstract: Embodiments of the disclosure are drawn to apparatuses and methods for automatic soft post-package repair (ASPPR). A memory may receive a row address along with a signal indicating an ASPPR operation, such as a bad page flag being set. A word line engine generates a physical address based on the row address, and ASPPR registers stores the physical address. The time it takes from receiving the row address to storing the physical address may be within the timing of an access operation on the memory such as tRAS. The row address may specify a single page of information. If the bad page flag is set, then a subsequent PPR operation may blow fuses to encode the physical address stored in the ASPPR registers.

公开(公告)号：US11335393B2

公开(公告)日：2022-05-17

申请号：US17173048

申请日：2021-02-10

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Yoshiro Riho ,  Yoshinori Matsui ,  Kiyohiro Furutani ,  Takahiko Fukiage ,  Ki-Jun Nam ,  John D. Porter

IPC: G11C11/406 ,  G11C11/4076 ,  G11C11/408

Abstract: Disclosed herein is an apparatus that includes a memory cell array including a plurality of memory cells, a first counter circuit configured to periodically update a count value during a first operation mode, a burst clock generator configured to successively generate a burst pulse predetermined times when the count value indicates a predetermined value, and a row address control circuit configured to perform a refresh operation on the memory cell array in response to the burst pulse.

公开(公告)号：US20210335399A1

公开(公告)日：2021-10-28

申请号：US17367060

申请日：2021-07-02

Applicant: Micron Technology, Inc.

Inventor： John D. Porter

IPC: G11C7/10 ,  G06F12/02

Abstract: An apparatus has a controller and an array of memory cells, including a first section comprising a plurality of rows and a second section comprising a plurality of rows. The controller configured to, in association with wear leveling, transfer data stored in a first row of the first section from the first row to a register, transfer the data from the register to a destination row of the second section while data in a second row of the first section is being sensed.

公开(公告)号：US20210304806A1

公开(公告)日：2021-09-30

申请号：US17208433

申请日：2021-03-22

Applicant: Micron Technology, Inc.

Inventor： Victor Wong ,  Sihong Kim ,  Hiroshi Akamatsu ,  Daniele Vimercati ,  John D. Porter

IPC: G11C11/22

Abstract: Methods, systems, and devices for temperature-based access timing for a memory device are described. In some memory devices, accessing memory cells may be associated with different operations that are variously dependent on a temperature of the memory device. For example, some operations associated with accessing a memory cell may have a longer duration and others a shorter duration depending on the temperature of the memory device. In accordance with examples as disclosed herein, a memory device may be configured for performing some portions of an access operation according to a duration that is proportional to a temperature of the memory device, and performing other portions of the access operation according to a duration that is inversely proportional to a temperature of the memory device.

公开(公告)号：US10923171B2

公开(公告)日：2021-02-16

申请号：US16163422

申请日：2018-10-17

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Yoshiro Riho ,  Yoshinori Matsui ,  Kiyohiro Furutani ,  Takahiko Fukiage ,  Ki-Jun Nam ,  John D. Porter

IPC: G11C11/406 ,  G11C11/4076 ,  G11C11/408

Abstract: Disclosed herein is an apparatus that includes a memory cell array including a plurality of memory cells, a first counter circuit configured to periodically update a count value during a first operation mode, a burst clock generator configured to successively generate a burst pulse predetermined times when the count value indicates a predetermined value, and a row address control circuit configured to perform a refresh operation on the memory cell array in response to the burst pulse.

公开(公告)号：US10910037B2

公开(公告)日：2021-02-02

申请号：US16152306

申请日：2018-10-04

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Dean D. Gans ,  John D. Porter

IPC: G06F3/06 ,  G06F13/40 ,  G11C11/4076 ,  G11C11/4074 ,  G06F13/16

Abstract: Apparatuses and methods for input receiver circuits and receiver masks for electronic memory are disclosed. Embodiments of the disclosure include memory receiver masks having shapes other than rectangular shapes. For example, a receiver mask according to some embodiments of the disclosure may have a hexagonal shape. Other shapes of receiver masks may also be included in other embodiments of the disclosure. Circuits, timing, and operating parameters for achieving non-rectangular and various shapes of receiver mask are described.

公开(公告)号：US20200251154A1

公开(公告)日：2020-08-06

申请号：US16856562

申请日：2020-04-23

Applicant: Micron Technology, Inc.

Inventor： John D. Porter

IPC: G11C7/10 ,  G06F12/02

Abstract: An apparatus has a controller and an array of memory cells, including a first section comprising a plurality of rows and a second section comprising a plurality of rows. The controller configured to, in association with wear leveling, transfer data stored in a first row of the first section from the first row to a register, transfer the data from the register to a destination row of the second section while data in a second row of the first section is being sensed.

公开(公告)号：US20200090709A1

公开(公告)日：2020-03-19

申请号：US16134732

申请日：2018-09-18

Applicant: Micron Technology, Inc.

Inventor： ADAM S. EL-MANSOURI ,  John D. Porter

IPC: G11C7/06 ,  G11C11/22 ,  G11C7/22 ,  G11C5/14

Abstract: Embodiments of the disclosure are drawn to apparatuses and methods for plate coupled sense amplifiers. An example embodiment may include a sense amplifier which may sense a voltage from a memory cell. The sense amplifier may also monitor a change in the voltage, and determine a logical value of the memory cell based on the time when the voltage reaches a trigger voltage. The memory cell may be coupled to a plate with a plate voltage, wherein a change in the plate voltage determines the change of the voltage from the memory cell.

公开(公告)号：US20190102109A1

公开(公告)日：2019-04-04

申请号：US15722769

申请日：2017-10-02

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Kang-Yong Kim ,  Hyun Yoo Lee ,  John D. Porter

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0611 ,  G06F3/0679 ,  G11C11/4074 ,  G11C11/4076 ,  G11C11/4085 ,  G11C11/4087

Abstract: Apparatuses and methods including memory commands for semiconductor memories are described. An example method includes receiving a data clock signal responsive to receiving a timing command, performing an access operation responsive to receiving an access command associated with the timing command, providing an access data clock signal based on the data clock signal, and providing an access data clock signal based on the data clock signal. The access command may be separated in time from the associated timing command by at least one clock cycle of a system clock signal. In some examples, the access command may precede the associated timing command or may follow the associated timing command. In some examples, the access command may immediately follow or precede the associated timing command.