公开(公告)号：US20150060754A1

公开(公告)日：2015-03-05

申请号：US14537670

申请日：2014-11-10

Applicant: Micron Technology, Inc.

Inventor： Jun Liu ,  Michael P. Violette

IPC: H01L45/00 ,  H01L27/24

CPC classification number: H01L45/1273 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/06 ,  H01L45/065 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/126 ,  H01L45/144 ,  H01L45/146 ,  H01L45/147 ,  H01L45/16 ,  H01L45/1675

Abstract: Memory devices having memory cells comprising variable resistance material include an electrode comprising a single nanowire. Various methods may be used to form such memory devices, and such methods may comprise establishing contact between one end of a single nanowire and a volume of variable resistance material in a memory cell. Electronic systems include such memory devices.

Abstract translation: 具有包含可变电阻材料的存储单元的存储器件包括包含单个纳米线的电极。 可以使用各种方法来形成这种存储器件，并且这样的方法可以包括建立单个纳米线的一端与存储器单元中的可变电阻材料体积之间的接触。 电子系统包括这样的存储器件。

公开(公告)号：US20140015001A1

公开(公告)日：2014-01-16

申请号：US14028242

申请日：2013-09-16

Applicant: Micron Technology, Inc.

Inventor： Sanh D. Tang ,  John K. Zahurak ,  Michael P. Violette

IPC: H01L29/74

CPC classification number: H01L29/66363 ,  H01L27/1027 ,  H01L29/42308 ,  H01L29/74 ,  H01L2924/1301

Abstract: Memory devices and methods of making memory devices are shown. Methods and configurations as shown provide folded and vertical memory devices for increased memory density. Methods provided reduce a need for manufacturing methods such as deep dopant implants.

Abstract translation: 显示存储器件和制造存储器件的方法。 所示的方法和配置提供用于增加存储器密度的折叠和垂直存储器件。 提供的方法减少了对诸如深掺杂剂植入物的制造方法的需要。

公开(公告)号：US20130230959A1

公开(公告)日：2013-09-05

申请号：US13861082

申请日：2013-04-11

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Sanh D. Tang ,  Michael P. Violette ,  Robert Burke

IPC: H01L29/78

CPC classification number: H01L29/7833 ,  G06K19/0723 ,  G06K19/0726 ,  G06K19/07771 ,  H01L21/76229 ,  H01L21/76232 ,  H01L21/76264 ,  H01L21/823418 ,  H01L21/823437 ,  H01L21/823481 ,  H01L21/823814 ,  H01L21/823828 ,  H01L29/1083 ,  H01L29/41783 ,  H01L29/66545 ,  H01L29/66583 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7834

Abstract: In one implementation, a method of forming a field effect transistor includes etching an opening into source/drain area of a semiconductor substrate. The opening has a base comprising semiconductive material. After the etching, insulative material is formed within the opening over the semiconductive material base. The insulative material less than completely fills the opening and has a substantially uniform thickness across the opening. Semiconductive source/drain material is formed within the opening over the insulative material within the opening. A transistor gate is provided operatively proximate the semiconductive source/drain material. Other aspects and implementations are contemplated.

Abstract translation: 在一个实施方案中，形成场效应晶体管的方法包括蚀刻半导体衬底的源/漏区的开口。 开口具有包括半导体材料的基底。 在蚀刻之后，在半导体材料基体的开口内形成绝缘材料。 绝缘材料小于完全填充开口并且在开口上具有基本均匀的厚度。 在开口内的绝缘材料的开口内形成半导电源极/漏极材料。 半导体源极/漏极材料可操作地提供晶体管栅极。 考虑了其他方面和实现。

公开(公告)号：US11424169B2

公开(公告)日：2022-08-23

申请号：US16535882

申请日：2019-08-08

Applicant: Micron Technology, Inc.

Inventor： Chiara Cerafogli ,  Kenneth William Marr ,  Brian J. Soderling ,  Michael P. Violette ,  Joshua Daniel Tomayer ,  James E. Davis

IPC: H01L23/528 ,  G11C16/26 ,  H01L21/66 ,  H01L23/00 ,  H01L27/11526 ,  H01L27/11573 ,  H03K3/03 ,  H01L27/11582 ,  G11C16/08 ,  G11C16/04 ,  G11C29/14 ,  H01L27/11556

Abstract: Some embodiments include apparatuses and methods of fabricating the apparatuses. One of the apparatuses includes a substrate of a semiconductor die; a memory cell portion located over a first portion of the substrate; a conductive pad portion located over a second portion of the substrate and outside the memory cell portion; and a sensor circuit including a portion located over the second portion of the substrate and under the conductive pad portion. The conductive pad portion includes conductive pads. Each of the conductive pads is part of a respective electrical path coupled to a conductive contact of a base outside the substrate.

公开(公告)号：US10777739B2

公开(公告)日：2020-09-15

申请号：US15850632

申请日：2017-12-21

Applicant: Micron Technology, Inc.

Inventor： Jun Liu ,  Michael P. Violette

IPC: H01L45/00

Abstract: Some embodiments include methods of forming memory cells. Such methods can include forming a first electrode, a second electrode, and a memory element directly contacting the first and second electrodes. Forming the memory element can include forming a programmable portion of the memory element isolated from the first electrode by a first portion of the memory element and isolated from the second electrode by a second portion of the memory element. Other embodiments are described.

公开(公告)号：US20180138399A1

公开(公告)日：2018-05-17

申请号：US15850632

申请日：2017-12-21

Applicant: Micron Technology, Inc.

Inventor： Jun Liu ,  Michael P. Violette

IPC: H01L45/00

Abstract: Some embodiments include methods of forming memory cells. Such methods can include forming a first electrode, a second electrode, and a memory element directly contacting the first and second electrodes. Forming the memory element can include forming a programmable portion of the memory element isolated from the first electrode by a first portion of the memory element and isolated from the second electrode by a second portion of the memory element. Other embodiments are described.

公开(公告)号：US09525131B2

公开(公告)日：2016-12-20

申请号：US14537670

申请日：2014-11-10

Applicant: Micron Technology, Inc.

Inventor： Jun Liu ,  Michael P. Violette

IPC: H01L45/00 ,  H01L27/24

CPC classification number: H01L45/1273 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/06 ,  H01L45/065 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/126 ,  H01L45/144 ,  H01L45/146 ,  H01L45/147 ,  H01L45/16 ,  H01L45/1675

Abstract: Memory devices having memory cells comprising variable resistance material include an electrode comprising a single nanowire. Various methods may be used to form such memory devices, and such methods may comprise establishing contact between one end of a single nanowire and a volume of variable resistance material in a memory cell. Electronic systems include such memory devices.

Abstract translation: 具有包含可变电阻材料的存储单元的存储器件包括包含单个纳米线的电极。 可以使用各种方法来形成这种存储器件，并且这样的方法可以包括建立单个纳米线的一端与存储器单元中的可变电阻材料体积之间的接触。 电子系统包括这样的存储器件。

公开(公告)号：US09472755B2

公开(公告)日：2016-10-18

申请号：US14617377

申请日：2015-02-09

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Jun Liu ,  Michael P. Violette

IPC: H01L45/00 ,  H01L27/24 ,  G11C13/00

CPC classification number: H01L45/1253 ,  G11C13/0004 ,  G11C13/0023 ,  G11C13/0026 ,  G11C13/003 ,  G11C2213/72 ,  G11C2213/74 ,  G11C2213/76 ,  G11C2213/78 ,  G11C2213/79 ,  H01L27/2409 ,  H01L27/2436 ,  H01L27/2472 ,  H01L27/2481 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144

Abstract: A resistive memory structure, for example, phase change memory structure, includes one access device and two or more resistive memory cells. Each memory cell is coupled to a rectifying device to prevent parallel leak current from flowing through non-selected memory cells. In an array of resistive memory bit structures, resistive memory cells from different memory bit structures are stacked and share rectifying devices.

公开(公告)号：US09461155B2

公开(公告)日：2016-10-04

申请号：US14028242

申请日：2013-09-16

Applicant: Micron Technology, Inc.

Inventor： Sanh D. Tang ,  John K. Zahurak ,  Michael P. Violette

IPC: H01L21/332 ,  H01L29/74 ,  H01L27/102 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L29/66363 ,  H01L27/1027 ,  H01L29/42308 ,  H01L29/74 ,  H01L2924/1301

Abstract: Memory devices and methods of making memory devices are shown. Methods and configurations as shown provide folded and vertical memory devices for increased memory density. Methods provided reduce a need for manufacturing methods such as deep dopant implants.

公开(公告)号：US20150380647A1

公开(公告)日：2015-12-31

申请号：US14844747

申请日：2015-09-03

Applicant: Micron Technology, Inc.

Inventor： Jun Liu ,  Michael P. Violette

IPC: H01L45/00 ,  H01L27/24

CPC classification number: H01L45/1608 ,  G11C13/0004 ,  G11C2213/72 ,  H01L27/101 ,  H01L27/24 ,  H01L27/2409 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/142 ,  H01L45/143 ,  H01L45/144

Abstract: Variable-resistance material memories include a buried salicide word line disposed below a diode. Variable-resistance material memories include a metal spacer spaced apart and next to the diode. Processes include the formation of one of the buried salicide word line and the metal spacer. Devices include the variable-resistance material memories and one of the buried salicided word line and the spacer word line.