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公开(公告)号:US20240321822A1
公开(公告)日:2024-09-26
申请号:US18668777
申请日:2024-05-20
Applicant: Micron Technology, Inc.
Inventor: Owen R. Fay , Madison E. Wale , James L. Voelz , Dylan W. Southern , Dustin L. Holloway
IPC: H01L23/00
CPC classification number: H01L24/82 , H01L24/20 , H01L24/29 , H01L24/45 , H01L24/83 , H01L24/85 , H01L2224/82203 , H01L2924/1431 , H01L2924/1434
Abstract: Semiconductor devices having redistribution structures, and associated systems and methods, are disclosed herein. In some embodiments, a semiconductor assembly comprises a die stack including a plurality of semiconductor dies, and a routing substrate mounted on the die stack. The routing substrate includes an upper surface having a redistribution structure. The semiconductor assembly also includes a plurality of electrical connectors coupling the redistribution structure to at least some of the semiconductor dies. The semiconductor assembly further includes a controller die mounted on the routing substrate. The controller die includes an active surface that faces the upper surface of the routing substrate and is electrically coupled to the redistribution structure, such that the routing substrate and the semiconductor dies are electrically coupled to the controller die via the redistribution structure.
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公开(公告)号:US20240304465A1
公开(公告)日:2024-09-12
申请号:US18668887
申请日:2024-05-20
Applicant: Micron Technology, Inc.
Inventor: Owen R. Fay , Chan H. Yoo
CPC classification number: H01L21/56 , H01L21/78 , H01L23/291 , H01L23/293 , H01L23/3114
Abstract: Methods for manufacturing semiconductor devices having a flexible reinforcement structure, and associated systems and devices, are disclosed herein. In one embodiment, a method of manufacturing a semiconductor device includes electrically coupling at least one semiconductor die to a redistribution structure on a first carrier. The semiconductor die can include a first surface facing the redistribution structure and a second surface spaced apart from the redistribution structure. The method also includes reducing a thickness of the semiconductor die to no more than 10 μm. The method further includes coupling a flexible reinforcement structure to the second surface of the at least one semiconductor die.
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公开(公告)号:US20230198139A1
公开(公告)日:2023-06-22
申请号:US18110872
申请日:2023-02-16
Applicant: Micron Technology, Inc.
Inventor: John F. Kaeding , Owen R. Fay
IPC: H01Q1/48
CPC classification number: H01Q1/48
Abstract: A method for tuning an antenna may include depositing multiple portions of an antenna structure onto a substrate. The method may further include electrically coupling each of the portions of the antenna structure. The method may also include severing an electrical connection between two of the portions of the antenna structure to tune the antenna structure for use with a transmission device.
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公开(公告)号:US20230197689A1
公开(公告)日:2023-06-22
申请号:US18169735
申请日:2023-02-15
Applicant: Micron Technology, Inc.
Inventor: Owen R. Fay , Kyle K. Kirby , Akshay N. Singh
IPC: H01L25/065 , H01L23/498 , H01L21/56 , H01L23/31
CPC classification number: H01L25/0657 , H01L23/49827 , H01L21/563 , H01L23/3114 , H01L2021/60037
Abstract: A semiconductor device assembly can include a first semiconductor device and an interposer. The interposer can include a substrate and through vias in which individual vias include an exposed portion and an embedded portion, the exposed portions projecting from one or both of the first surface and the second surface of the substrate, and the embedded portions extending through at least a portion of the substrate. The interposer can include one or more test pads, a first electrical contact, and a second electrical contact. The semiconductor device assembly can include a controller positioned on an opposite side of the interposer from the first semiconductor device and operably coupled to the interposer via connection to the second electrical contact.
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公开(公告)号:US20230008292A1
公开(公告)日:2023-01-12
申请号:US17932401
申请日:2022-09-15
Applicant: Micron Technology, Inc.
Inventor: Randon K. Richards , Aparna U. Limaye , Owen R. Fay , Dong Soon Lim
IPC: H01L25/065 , H01L25/18 , H01L23/00 , H01L23/552 , H01L23/64 , H01L21/78 , H01L21/66 , H01L25/00 , H01L23/66 , H01Q1/22 , H01Q1/48
Abstract: Disclosed is a microelectronic device assembly comprising a substrate having conductors exposed on a surface thereof. Two or more microelectronic devices are stacked on the substrate and the components are connected with conductive material in preformed holes in dielectric material in the bond lines aligned with TSVs of the devices and the exposed conductors of the substrate. Methods of fabrication are also disclosed.
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公开(公告)号:US20220375902A1
公开(公告)日:2022-11-24
申请号:US17817690
申请日:2022-08-05
Applicant: Micron Technology, Inc.
Inventor: Owen R. Fay , Randon K. Richards , Aparna U. Limaye , Dong Soon Lim , Chan H. Yoo , Bret K. Street , Eiichi Nakano , Shijian Luo
IPC: H01L25/065 , H01L25/18 , H01L23/00 , H01L23/552 , H01L23/64 , H01L21/78 , H01L21/66 , H01L25/00 , H01L23/66 , H01Q1/22 , H01Q1/48
Abstract: Disclosed is a microelectronic device assembly comprising a substrate having conductors exposed on a surface thereof. Two or more microelectronic devices are stacked on the substrate, each microelectronic device comprising an active surface having bond pads operably coupled to conductive traces extending over a dielectric material to via locations beyond at least one side of the stack, and vias extending through the dielectric materials at the via locations and comprising conductive material in contact with at least some of the conductive traces of each of the two or more electronic devices and extending to exposed conductors of the substrate. Methods of fabrication and related electronic systems are also disclosed.
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37.
公开(公告)号:US20220302090A1
公开(公告)日:2022-09-22
申请号:US17805818
申请日:2022-06-07
Applicant: Micron Technology, Inc
Inventor: Aparna U. Limaye , Dong Soon Lim , Randon K. Richards , Owen R. Fay
IPC: H01L25/065 , H01L25/18 , H01L23/00 , H01L23/552 , H01L23/64 , H01L21/78 , H01L21/66 , H01L25/00 , H01L23/66 , H01Q1/22 , H01Q1/48
Abstract: Disclosed is a microelectronic device assembly comprising a substrate having conductors exposed on a surface thereof. Two or more stacks of microelectronic devices are located on the substrate, and microelectronic devices of the stacks are connected to vertical conductive paths external to the stacks and extending to the substrate and to lateral conductive paths extending between the stacks. Methods of fabrication are also disclosed.
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38.
公开(公告)号:US20220208736A1
公开(公告)日:2022-06-30
申请号:US17697141
申请日:2022-03-17
Applicant: Micron Technology, Inc.
Inventor: Owen R. Fay , Chan H. Yoo , Mark E. Tuttle
IPC: H01L25/065 , H01L21/56 , H01L23/31 , H01L23/532 , H01L23/00
Abstract: Semiconductor device packages and associated assemblies are disclosed herein. In some embodiments, the semiconductor device package includes a substrate having a first side and a second side opposite the first side, a first metallization layer positioned at the first side of the substrate, and a second metallization layer in the substrate and electrically coupled to the first metallization layer. The semiconductor device package further includes a metal bump electrically coupled to the first metallization layer and a divot formed at the second side of the substrate and aligned with the metal bump. The divot exposes a portion of the second metallization layer and enables the portion to electrically couple to another semiconductor device package.
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39.
公开(公告)号:US11276658B2
公开(公告)日:2022-03-15
申请号:US16987223
申请日:2020-08-06
Applicant: Micron Technology, Inc.
Inventor: Christopher J. Gambee , Nhi Doan , Chandra S. Tiwari , Owen R. Fay , Ying Chen
IPC: H01L23/00 , H01L21/027 , H01L21/56
Abstract: Methods of forming supports for 3D structures on semiconductor structures comprise forming the supports from photodefinable materials by deposition, selective exposure and curing. Semiconductor dice including 3D structures having associated supports, and semiconductor devices are also disclosed.
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公开(公告)号:US20220028820A1
公开(公告)日:2022-01-27
申请号:US17490224
申请日:2021-09-30
Applicant: Micron Technology, Inc.
Inventor: Mark E. Tuttle , John F. Kaeding , Owen R. Fay , Eiichi Nakano , Shijian Luo
IPC: H01L23/00
Abstract: A semiconductor device assembly has a first substrate, a second substrate, and an anisotropic conductive film. The first substrate includes a first plurality of connectors. The second substrate includes a second plurality of connectors. The anisotropic conductive film is positioned between the first plurality of connectors and the second plurality of connectors. The anisotropic conductive film has an electrically insulative material and a plurality of interconnects laterally separated by the electrically insulative material. The plurality of interconnects forms electrically conductive channels extending from the first plurality of connectors to the second plurality of connectors. A method includes connecting the plurality of interconnects to the first plurality of connectors and the second plurality of connectors, such that the electrically conductive channels are operable to conduct electricity from the first substrate to the second substrate. The method may include passing electrical current through the plurality of interconnects.
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