公开(公告)号：US20250104781A1

公开(公告)日：2025-03-27

申请号：US18973880

申请日：2024-12-09

Applicant: Micron Technology, Inc.

Inventor： Violante Moschiano ,  Shyam Sunder Raghunathan ,  Walter Di Francesco

IPC: G11C16/32 ,  G11C16/08 ,  G11C16/10

Abstract: A memory device includes an array of memory cells associated with multiple wordlines and control logic operatively coupled with the array. The control logic, in performing a read operation, can determine a length of time that a selected wordline, of the multiple wordlines, takes to reach a pass voltage for reading data from a memory cell associated with the selected wordline. The control logic can select a delay time based on whether the length of time is associated with a transient state or a non-transient state. The control logic can read the data from the memory cell associated with the selected wordline after the selected delay time.

公开(公告)号：US12165688B2

公开(公告)日：2024-12-10

申请号：US17747183

申请日：2022-05-18

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Yankang He ,  Walter Di Francesco ,  Luca Nubile ,  Chang Siau

IPC: G11C11/406 ,  G11C11/4072 ,  G11C11/4094

Abstract: One example of a memory device includes an array of flash memory cells, an array of Dynamic Random Access Memory (DRAM) memory cells, and a controller. The controller is configured to execute first instructions stored in the array of DRAM memory cells to access the array of flash memory cells.

公开(公告)号：US12086427B2

公开(公告)日：2024-09-10

申请号：US17677641

申请日：2022-02-22

Applicant: Micron Technology, Inc.

Inventor： Sriteja Yamparala ,  Fulvio Rori ,  Marco Domenico Tiburzi ,  Walter Di Francesco ,  Chiara Cerafogli ,  Tawalin Opastrakoon

IPC: G06F1/28 ,  G06F1/08 ,  G06F3/06

CPC classification number: G06F3/0625 ,  G06F1/08 ,  G06F1/28 ,  G06F3/0653 ,  G06F3/0673

Abstract: Various embodiments of the present disclosure relate to monitoring the integrity of power signals within memory systems. A method can include receiving a power signal at a memory component, and monitoring, via a power signal monitoring component of the memory component, an integrity characteristic of the power signal. Responsive to the integrity characteristic meeting a particular criteria, the method can include providing a status indication to a control component external to the memory component.

公开(公告)号：US12068034B2

公开(公告)日：2024-08-20

申请号：US17899409

申请日：2022-08-30

Applicant: Micron Technology, Inc.

Inventor： Kishore Kumar Muchherla ,  Huai-Yuan Tseng ,  Giovanni Maria Paolucci ,  Dave Scott Ebsen ,  James Fitzpatrick ,  Akira Goda ,  Jeffrey S. McNeil ,  Umberto Siciliani ,  Daniel J. Hubbard ,  Walter Di Francesco ,  Michele Incarnati

IPC: G11C16/10 ,  G11C16/08 ,  G11C16/34

CPC classification number: G11C16/102 ,  G11C16/08 ,  G11C16/3404

Abstract: Exemplary methods, apparatuses, and systems including a programming manager for controlling writing data bits to a memory device. The programming manager receives a first set of data bits for programming to memory. The programming manager writes a first subset of data bits to a first wordline during a first pass of programming. The programming manager writes a second subset of data bits of the first set of data bits to a buffer. The programming manager receives a second set of data bits for programming. The programming manager writes the second subset of data bits of the first set of data bits to the first wordline during a second pass of programming to increase a bit density of memory cells in the first wordline in response to receiving the second set of data bits.

公开(公告)号：US20240272812A1

公开(公告)日：2024-08-15

申请号：US18621747

申请日：2024-03-29

Applicant: Micron Technology, Inc.

Inventor： Luca Nubile ,  Walter Di Francesco ,  Fumin Gu ,  Ali Mohammadzadeh ,  Biagio Iorio ,  Liang Yu

IPC: G06F3/06

CPC classification number: G06F3/0625 ,  G06F3/0653 ,  G06F3/0659 ,  G06F3/0679

Abstract: A memory device includes a memory array and control logic, operatively coupled with the memory array. The control logic allocates power to one or more prioritized processing threads, of a plurality of processing threads that access the memory array, based on a value of a priority ring counter. The control logic starts a timer in response to detecting allocation of the power to a non-prioritized processing thread of the plurality of processing threads. While the timer is running, the control logic increments the priority ring counter before each power management cycle and prioritizes allocation of the power to the one or more prioritized processing threads located within a subset of the plurality of processing threads corresponding to a value of the priority ring counter.

公开(公告)号：US20240241643A1

公开(公告)日：2024-07-18

申请号：US18407239

申请日：2024-01-08

Applicant: Micron Technology, Inc.

Inventor： Biagio Iorio ,  Luca Nubile ,  Walter Di Francesco ,  Jeremy Binfet ,  Liang Yu ,  Yankang He ,  Ali Mohammadzadeh

IPC: G06F3/06

CPC classification number: G06F3/061 ,  G06F3/0659 ,  G06F3/0679

Abstract: Control logic on a memory die of a multi-die memory sub-system receives, from a memory sub-system controller, a data burst command indicating an upcoming data burst event and determines an expected current utilization in the memory sub-system during the data burst event. The control logic further determines whether the expected current utilization in the memory sub-system during the data burst event satisfies a threshold criterion and responsive to determining that the expected current utilization in the memory sub-system during the data burst event does not satisfy the threshold criterion, pauses one or more operations being executed by the control logic on the memory die until the expected current utilization in the memory sub-system during the data burst event satisfies the threshold criterion. Responsive to determining that the expected current utilization in the memory sub-system during the data burst event satisfies the threshold criterion, the control logic provides, to the memory sub-system controller, an indication that the data burst event is approved and can perform one or more operations corresponding to the data burst event.

公开(公告)号：US11977748B2

公开(公告)日：2024-05-07

申请号：US17668311

申请日：2022-02-09

Applicant: Micron Technology, Inc.

Inventor： Luca Nubile ,  Walter Di Francesco ,  Fumin Gu ,  Ali Mohammadzadeh ,  Biagio Iorio ,  Liang Yu

IPC: G06F3/06

CPC classification number: G06F3/0625 ,  G06F3/0653 ,  G06F3/0659 ,  G06F3/0679

Abstract: A memory device includes memory dice, each memory die including: a memory array; a memory to store a data structure; and control logic that includes: multiple processing threads to execute memory access operations on the memory array concurrently; a priority ring counter, the data structure to store an association between a value of the priority ring counter and a subset of the multiple processing threads; a threads manager to increment the value of the priority ring counter before a power management cycle and to identify one or more prioritized processing threads corresponding to the subset of the multiple processing threads; and a peak power manager coupled with the threads manager and to prioritize allocation of power to the one or more prioritized processing threads during the power management cycle.

公开(公告)号：US11908523B2

公开(公告)日：2024-02-20

申请号：US17675526

申请日：2022-02-18

Applicant: Micron Technology, Inc.

Inventor： Walter Di Francesco ,  Violante Moschiano ,  Umberto Siciliani

IPC: G11C16/10 ,  G11C16/04 ,  G06F12/0802 ,  G11C11/56

CPC classification number: G11C16/10 ,  G06F12/0802 ,  G11C16/0483 ,  G06F2212/60 ,  G06F2212/72 ,  G11C11/56

Abstract: Control logic in a memory device initiates an express programming operation to program the set of memory cells to a target programming level of a set of programming levels. A set of data associated with the express programming operation is stored in a cache register. At a first time during the execution of the express programming operation, a prediction operation is executed to determine a prediction result corresponding to a programming status of the set of memory cells. The prediction result is compared to a threshold level to determine whether a condition is satisfied. The release of the set of data from the cache register is caused in response to satisfying the condition.

公开(公告)号：US20230197169A1

公开(公告)日：2023-06-22

申请号：US18083304

申请日：2022-12-16

Applicant: Micron Technology, Inc.

Inventor： Violante Moschiano ,  Shyam Sunder Raghunathan ,  Walter Di Francesco

IPC: G11C16/32 ,  G11C16/10 ,  G11C16/08

CPC classification number: G11C16/32 ,  G11C16/102 ,  G11C16/08

Abstract: A memory device includes an array of memory cells arranged in sub-blocks. Memory cells of a sub-block are coupled to a pillar of the array and are associated with multiple wordlines. To perform a read operation, control logic coupled with the array performs operations including: tracking a length of time that a selected wordline takes to reach a pass voltage before being able to read data from a memory cell associated with the selected wordline; in response to the length of time satisfying a first threshold criterion, causing a first delay time to pass before reading the data; and in response to the length of time satisfying a second threshold criterion that is longer than the first threshold criterion, causing a second delay time to pass before reading the data, the second delay time being longer than the first delay time.

公开(公告)号：US20230084630A1

公开(公告)日：2023-03-16

申请号：US17668311

申请日：2022-02-09

Applicant: Micron Technology, Inc.

Inventor： Luca Nubile ,  Walter Di Francesco ,  Fumin Gu ,  Ali Mohammadzadeh ,  Biagio Iorio ,  Liang Yu

IPC: G06F3/06

Abstract: A memory device includes memory dice, each memory die including: a memory array; a memory to store a data structure; and control logic that includes: multiple processing threads to execute memory access operations on the memory array concurrently; a priority ring counter, the data structure to store an association between a value of the priority ring counter and a subset of the multiple processing threads; a threads manager to increment the value of the priority ring counter before a power management cycle and to identify one or more prioritized processing threads corresponding to the subset of the multiple processing threads; and a peak power manager coupled with the threads manager and to prioritize allocation of power to the one or more prioritized processing threads during the power management cycle.