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    METHODS OF FORMING SEMICONDUCTOR PATTERNS INCLUDING REDUCED DISLOCATION DEFECTS AND DEVICES FORMED USING SUCH METHODS
    33.
    发明申请
    METHODS OF FORMING SEMICONDUCTOR PATTERNS INCLUDING REDUCED DISLOCATION DEFECTS AND DEVICES FORMED USING SUCH METHODS 有权
    形成半导体图案的方法，包括减少的偏差缺陷和使用这种方法形成的器件

    公开(公告)号：US20150093884A1

    公开(公告)日：2015-04-02

    申请号：US14258704

    申请日：2014-04-22

    Applicant: Wei-E Wang ,  Mark S. Rodder ,  Robert C. Bowen

    Inventor： Wei-E Wang ,  Mark S. Rodder ,  Robert C. Bowen

    IPC: H01L21/02 ,  H01L21/762

    CPC classification number: H01L21/02488 ,  H01L21/02532 ,  H01L21/02538 ,  H01L21/02546 ,  H01L21/02639 ,  H01L21/02647 ,  H01L29/66795

    Abstract: Methods of forming semiconductor patterns including reduced dislocation defects and devices formed using such methods are provided. The methods may include forming an oxide layer on a substrate and forming a recess in the oxide layer and the substrate. The methods may further include forming an epitaxially grown semiconductor pattern in the recess that contacts a sidewall of the substrate at an interface between the oxide layer and the substrate and defines an upper surface of a void in the recess in the substrate.

    Abstract translation: 提供了形成包括减少的位错缺陷的半导体图案的方法和使用这些方法形成的器件。 所述方法可以包括在衬底上形成氧化物层并在氧化物层和衬底中形成凹陷。 所述方法还可以包括在所述凹部中形成外延生长的半导体图案，所述外延生长的半导体图案在所述氧化物层和所述衬底之间的界面处接触所述衬底的侧壁，并且限定所述衬底的所述凹部中的空隙的上表面。

    Process of increasing screen dielectric thickness
    36.
    发明授权
    Process of increasing screen dielectric thickness 有权
    屏幕介电厚度增加的过程

    公开(公告)号：US06723616B2

    公开(公告)日：2004-04-20

    申请号：US10253870

    申请日：2002-09-24

    Applicant: Seetharaman Sridhar ,  Youngmin Kim ,  Zhiqiang Wu ,  Mark S. Rodder

    Inventor： Seetharaman Sridhar ,  Youngmin Kim ,  Zhiqiang Wu ,  Mark S. Rodder

    IPC: H01L2176

    CPC classification number: H01L21/76232

    Abstract: A method of forming a semiconductor device using shallow trench isolation, includes forming a trench within a semiconductor substrate and forming a screen dielectric stack outwardly from the semiconductor substrate. The screen dielectric stack includes a first sacrificial dielectric layer disposed outwardly from the semiconductor substrate and a second sacrificial dielectric layer disposed outwardly from and in contact with the first sacrificial dielectric layer. In one embodiment, the first sacrificial dielectric layer is formed before forming the trench and the second sacrificial dielectric layer is formed after forming the trench.

    Abstract translation: 使用浅沟槽隔离来形成半导体器件的方法包括在半导体衬底内形成沟槽并从半导体衬底向外形成屏蔽电介质堆叠。 屏幕电介质堆叠包括从半导体衬底向外设置的第一牺牲电介质层和从第一牺牲介电层向外设置并与之接触的第二牺牲电介质层。 在一个实施例中，在形成沟槽之前形成第一牺牲电介质层，并且在形成沟槽之后形成第二牺牲绝缘层。

    Shallow-implant elevated source/drain doping from a sidewall dopant source
    37.
    发明授权
    Shallow-implant elevated source/drain doping from a sidewall dopant source 有权
    浅植入物从侧壁掺杂剂源提高源极/漏极掺杂

    公开(公告)号：US06346447B1

    公开(公告)日：2002-02-12

    申请号：US09335357

    申请日：1999-06-17

    Applicant: Mark S. Rodder

    Inventor： Mark S. Rodder

    IPC: H01L21336

    CPC classification number: H01L29/6659 ,  H01L29/41783 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/7834

    Abstract: A structure having shallow-implanted elevated source/drain regions is formed with doped sidewall spacers. Diffusion of dopants from the sidewall spacers forms a doped region extending from underneath the gate electrode, along the edge of the epitaxial layer, to the doped (and uppermost) regions of the elevated source/drain. Low junction capacitance, is achieved because the shallow implant of the elevated source/drain regions places the junction inside the source/drain region itself. Low source/drain resistance is achieved because the diffused doped region provides a doped path between the shallow implanted region of the elevated source/drain and the channel region. Low source/drain junction depth is achieved because a second spacer can prevent dopant from being implanted through any faceted areas of the epitaxial layer. The doped extensions of the source/drain regions also have exceptionally low junction depth. The overall process is simpler because it is independent of both facet angle and height of the epitaxial layer.

    Abstract translation: 具有浅注入的升高的源极/漏极区域的结构形成有掺杂的侧壁间隔物。 来自侧壁间隔物的掺杂剂的扩散形成从栅电极下方沿着外延层的边缘延伸到升高的源极/漏极的掺杂（和最上）区域的掺杂区域。 低结电容是实现的，因为升高的源极/漏极区域的浅埋入使得接头在源/漏区本身内部。 实现低的源极/漏极电阻，因为扩散掺杂区域在升高的源极/漏极的浅注入区域和沟道区域之间提供掺杂路径。 实现了低源极/漏极结深度，因为第二间隔物可以防止掺杂剂通过外延层的任何刻面区域被注入。 源极/漏极区域的掺杂延伸部分也具有非常低的结深度。 整个过程更简单，因为它独立于外延层的面角和高度。

    Shallow-implant elevated source/drain doping from a sidewall dopant source
    40.
    发明授权
    Shallow-implant elevated source/drain doping from a sidewall dopant source 有权

    公开(公告)号：US06160299A

    公开(公告)日：2000-12-12

    申请号：US140036

    申请日：1998-08-26

    Applicant: Mark S. Rodder

    Inventor： Mark S. Rodder

    IPC: H01L21/336 ,  H01L29/78 ,  H01L31/119

    CPC classification number: H01L29/6659 ,  H01L29/41783 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/7834

    Abstract: A structure having shallow-implanted elevated source/drain regions is formed with doped sidewall spacers. Diffusion of dopants from the sidewall spacers forms a doped region extending from underneath the gate electrode, along the edge of the epitaxial layer, to the doped (and uppermost) regions of the elevated source/drain. Low junction capacitance, is achieved because the shallow implant of the elevated source/drain regions places the junction inside the source/drain region itself. Low source/drain resistance is achieved because the diffused doped region provides a doped path between the shallow implanted region of the elevated source/drain and the channel region. Low source/drain junction depth is achieved because a second spacer can prevent dopant from being implanted through any faceted areas of the epitaxial layer. The doped extensions of the source/drain regions also have exceptionally low junction depth. The overall process is simpler because it is independent of both facet angle and height of the epitaxial layer.

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