公开(公告)号：US06953696B2

公开(公告)日：2005-10-11

申请号：US10959972

申请日：2004-10-08

申请人： Hiroyuki Yamauchi

发明人： Hiroyuki Yamauchi

IPC分类号： H01L21/027 ,  H01L21/28 ,  H01L21/3205 ,  H01L21/66 ,  H01L21/768 ,  H01L21/822 ,  H01L21/8234 ,  H01L27/04 ,  H01L27/088 ,  H01L21/00

CPC分类号： H01L22/20 ,  H01L21/28017 ,  H01L21/76819 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for fabricating a semiconductor integrated circuit device of the present invention forms an insulating film on a semiconductor wafer and forms a mask pattern containing a functional element or a wire on the formed insulating film. Dimensions of the mask pattern are changed in accordance with an amount of process variation occurring in the thickness or dielectric constant of the insulating film during the formation of the insulating film.

摘要翻译： 本发明的半导体集成电路器件的制造方法在半导体晶片上形成绝缘膜，并在形成的绝缘膜上形成包含功能元件或线的掩模图案。 根据在形成绝缘膜期间绝缘膜的厚度或介电常数发生的工艺变化量，改变掩模图案的尺寸。

公开(公告)号：US20050095832A1

公开(公告)日：2005-05-05

申请号：US10959972

申请日：2004-10-08

申请人： Hiroyuki Yamauchi

发明人： Hiroyuki Yamauchi

IPC分类号： H01L21/027 ,  H01L21/28 ,  H01L21/3205 ,  H01L21/66 ,  H01L21/768 ,  H01L21/822 ,  H01L21/8234 ,  H01L27/04 ,  H01L27/088 ,  H01L21/76 ,  H01L21/4763

CPC分类号： H01L22/20 ,  H01L21/28017 ,  H01L21/76819 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for fabricating a semiconductor integrated circuit device of the present invention forms an insulating film on a semiconductor wafer and forms a mask pattern containing a functional element or a wire on the formed insulating film. Dimensions of the mask pattern are changed in accordance with an amount of process variation occurring in the thickness or dielectric constant of the insulating film during the formation of the insulating film.

公开(公告)号：US06768334B1

公开(公告)日：2004-07-27

申请号：US09553308

申请日：2000-04-20

申请人： Hiroyuki Yamauchi ,  Tadahiro Yoshida

发明人： Hiroyuki Yamauchi ,  Tadahiro Yoshida

IPC分类号： H03K19003

CPC分类号： H01P5/02

摘要： A signal transmitting/receiving apparatus according to the present invention includes: a transmitting device for transmitting data; a receiving device for receiving the data; a data line for transmitting the data; and a supply line for transmitting a bias voltage for determining a voltage of the data line, wherein the transmitting device and the receiving device are connected to each other through the data line and the supply line, the transmitting device including: a driver circuit for outputting the data to the data lines and a bias generating means for generating the bias voltage and outputting the bias voltage to the supply line, the receiving device including: a terminating resistor connected to the data line; and a receiver circuit for detecting the data from the data line, wherein the data line is connected to the supply line via the terminating resistor.

摘要翻译： 根据本发明的信号发送/接收装置包括：发送装置，用于发送数据; 用于接收数据的接收装置; 用于发送数据的数据线; 以及用于发送用于确定数据线的电压的偏置电压的电源线，其中所述发送装置和所述接收装置通过所述数据线和所述供给线彼此连接，所述发送装置包括：驱动器电路，用于输出 数据线路的数据和偏置产生装置，用于产生偏置电压并将偏置电压输出到电源线，所述接收装置包括：连接到数据线的终端电阻; 以及用于检测来自数据线的数据的接收器电路，其中数据线经由终端电阻器连接到电源线。

公开(公告)号：US06542401B2

公开(公告)日：2003-04-01

申请号：US10043134

申请日：2002-01-14

申请人： Hiroyuki Yamauchi ,  Yoshinori Yamagami

发明人： Hiroyuki Yamauchi ,  Yoshinori Yamagami

IPC分类号： G11C1100

CPC分类号： G11C11/419 ,  G11C7/12 ,  G11C11/412 ,  H01L27/1104

摘要： An SRAM device of the present invention is an SRAM device, including: a plurality of bit line pairs that are arranged substantially parallel to one another and connected to different memory cells, respectively; selection means for selecting one bit line pair from among the plurality of bit line pairs; and potential holding means for holding a precharge potential of bit lines that are respectively on opposite sides of the one bit line pair with the one bit line pair being selected, wherein an interval between two adjacent bit line pairs is smaller than an interval between two bit lines of the same bit line pair.

公开(公告)号：US06429060B1

公开(公告)日：2002-08-06

申请号：US09934538

申请日：2001-08-23

申请人： Kazuo Itoh ,  Hiroyuki Yamauchi

发明人： Kazuo Itoh ,  Hiroyuki Yamauchi

IPC分类号： H01L21336

CPC分类号： H01L21/76838 ,  H01L21/28123 ,  H01L21/76802 ,  Y10S438/926

摘要： The accuracy in forming a gate electrode or an interconnect is improved by using a dummy gate electrode or a dummy interconnect. In addition, the dummy gate electrode or the dummy interconnect is removed, so that a region where the dummy gate electrode or the dummy interconnect has been disposed can be used as a region for forming another composing element.

公开(公告)号：US06323756B1

公开(公告)日：2001-11-27

申请号：US09486868

申请日：2000-05-26

申请人： Takefumi Yoshikawa ,  Toru Iwata ,  Hiroyuki Yamauchi

发明人： Takefumi Yoshikawa ,  Toru Iwata ,  Hiroyuki Yamauchi

IPC分类号： H04M1104

CPC分类号： H03K19/017545 ,  H03K19/0013

摘要： The data transmission device 1a of the present invention includes a driver 10 for sending data, a receiver 20 for receiving the data sent from the driver 10, a transmission line path 30 for connecting between the driver 10 and the receiver 20, and a variable impedance element 40 having a controllably variable impedance. The variable impedance element 40 is connected to the transmission line path 30. The data transmission line device 1a can reduce power consumption and occurrence of skew.

摘要翻译： 本发明的数据传输装置1a包括用于发送数据的驱动器10，用于接收从驱动器10发送的数据的接收器20，用于连接驱动器10和接收器20的传输线路径30和可变阻抗 元件40具有可控制的可变阻抗。 可变阻抗元件40连接到传输线路径30.数据传输线设备1a可以降低功耗并产生偏斜。

公开(公告)号：US5929687A

公开(公告)日：1999-07-27

申请号：US744664

申请日：1996-11-06

申请人： Hiroyuki Yamauchi

发明人： Hiroyuki Yamauchi

IPC分类号： H03K19/00 ,  H04L25/02 ,  H03L5/00

CPC分类号： H04L25/0292 ,  H04L25/0272 ,  H04L25/028

摘要： In transmitting a first pair of differential clock signals UCLK, UXCLK having an extremely small amplitude voltage based on a power-source potential and a second pair of differential clock signals LCLK, LXCLK having an extremely small amplitude voltage based on the power-source potential, an inverting circuit as a signal receiving circuit is composed of a CMOS inverting circuit. A PMOS transistor composing the CMOS inverting circuit has a gate electrode and a source electrode receiving the first pair of differential clock signals. An NMOS transistor composing the CMOS inverting circuit has a gate electrode and a source electrode receiving the second pair of differential clock signals. When the potentials of the differential clock signals change, potentials at the respective gate and source electrodes of the two transistors shift in opposite directions, which surely cuts off the transistors. Accordingly, the signal receiving circuit composed of the inverting circuit operates statically in response to the first and second pairs of differential signals.

公开(公告)号：US5748520A

公开(公告)日：1998-05-05

申请号：US741618

申请日：1996-10-31

申请人： Hideo Asaka ,  Hiroyuki Yamauchi

发明人： Hideo Asaka ,  Hiroyuki Yamauchi

IPC分类号： G11C8/08 ,  G11C11/408 ,  G11C11/4094 ,  G11C29/02 ,  G11C29/50 ,  G11C11/24

CPC分类号： G11C11/4094 ,  G11C11/4085 ,  G11C29/02 ,  G11C29/50 ,  G11C8/08 ,  G11C11/401

摘要： Precharge circuits precharge plural pairs of bit lines to a specified potential when no word line is selected (during standby). Pull-down transistors are turned ON when the corresponding word lines are not selected so as to connect the corresponding word lines to a common power source line, which is connected to the ground. In a path connecting the above common power source line to the ground is disposed an impedance changing means for changing the impedance of the path between a value during standby and another value during operation during which any word line is selected so that the value during standby is set higher than the value during operation. Consequently, during standby, a leakage current (standby current) resulting from a short circuit between a bit line and a word line is reduced.

摘要翻译： 当没有选择字线（待机）时，预充电电路将多对位线预充电到指定的电位。 当对应的字线未被选择时，下拉晶体管导通，以将相应的字线连接到连接到地的公共电源线。 在将上述公共电源线连接到地线的路径中设置有阻抗改变装置，用于改变在待机期间的路径之间的路径阻抗和操作期间的另一个值，在此期间选择任何字线，使得待机期间的值为 设置高于操作期间的值。 因此，在待机期间，由位线和字线之间的短路引起的漏电流（待机电流）减小。

公开(公告)号：US5680356A

公开(公告)日：1997-10-21

申请号：US684068

申请日：1996-07-19

申请人： Hiroyuki Yamauchi

发明人： Hiroyuki Yamauchi

IPC分类号： G11C11/412 ,  G11C11/417 ,  G11C11/419 ,  G11C7/00

CPC分类号： G11C11/417 ,  G11C11/412 ,  G11C11/419

摘要： A memory cell is formed by flip-flop connection of a load transistor pair of a first load transistor and a second load transistor and a drive transistor pair of a first drive transistor and a second drive transistor. A first switch which is controlled by a wordline and a second switch which is activated only at the time of the write operation are connected in series to a first memory node. The second switch is serially coupled between the first memory node and the first drive transistor. An electric current is injected from a sense amplifier into a bitline pair selected at the time of the read operation, to detect an impedance which varies with the signal potential at the first memory node.

摘要翻译： 通过第一负载晶体管和第二负载晶体管的负载晶体管对和第一驱动晶体管和第二驱动晶体管的驱动晶体管对的触发器连接来形成存储单元。 由字线控制的第一开关和仅在写操作时被激活的第二开关被串联连接到第一存储器节点。 第二开关串联耦合在第一存储器节点和第一驱动晶体管之间。 从读出放大器将电流注入到在读取操作时选择的位线对，以检测随着第一存储节点处的信号电位而变化的阻抗。

公开(公告)号：US5389841A

公开(公告)日：1995-02-14

申请号：US114142

申请日：1993-09-01

申请人： Masashi Agata ,  Hiroyuki Yamauchi ,  Atsushi Fujiwara

发明人： Masashi Agata ,  Hiroyuki Yamauchi ,  Atsushi Fujiwara

IPC分类号： G11C7/10 ,  G11C11/419 ,  H03H17/00

CPC分类号： G11C7/1057 ,  G11C11/419 ,  G11C7/1048 ,  G11C7/1051 ,  G11C7/1069 ,  Y10T307/516

摘要： In a MOS integrated circuit is provided a first differential amplifying circuit for receiving complementary sets of input data at the gates of its two p-channel MOS transistors and for transmitting complementary sets of internal data. There is also provided a second differential amplifying circuit for receiving the complementary sets of internal data at the gates of its two n-channel MOS transistors and for transmitting complementary sets of output data. This realizes high-speed data transmission in which data transmission speed is independent of the generation of a clock signal. By preventing the flow of current from a power supply terminal to a ground terminal, a differential transmission circuit which consumes reduced current can be obtained.

摘要翻译： 在MOS集成电路中提供有第一差分放大电路，用于在其两个p沟道MOS晶体管的栅极处接收互补的输入数据组，并用于发送互补的内部数据集。 还提供了一个第二差分放大电路，用于在其两个n沟道MOS晶体管的栅极处接收互补的内部数据组，并用于传输补充的输出数据组。 这实现了数据传输速度与时钟信号的产生无关的高速数据传输。 通过防止从电源端子到接地端子的电流流动，可以获得消耗电流降低的差分传输电路。