公开(公告)号：US20190273120A1

公开(公告)日：2019-09-05

申请号：US16253111

申请日：2019-01-21

Applicant: Micron Technology, Inc.

Inventor： Fatma Arzum Simsek-Ege ,  Krishna K. Parat

IPC: H01L27/24 ,  H01L45/00 ,  H01L27/11553 ,  H01L27/1158 ,  H01L29/788 ,  H01L29/66 ,  H01L29/792

Abstract: Various embodiments comprise apparatuses and methods, such as a memory stack having a continuous cell pillar. In various embodiments, the apparatus includes a source material, a buffer material, a select gate drain (SGD), and a memory stack arranged between the source material and the SGD. The memory stack comprises alternating levels of conductor materials and dielectric materials. A continuous channel-fill material forms a cell pillar that is continuous from the source material to at least a level corresponding to the SGD.

公开(公告)号：US10170491B2

公开(公告)日：2019-01-01

申请号：US15410469

申请日：2017-01-19

Applicant: Micron Technology, Inc.

Inventor： Fatma Arzum Simsek-Ege ,  John Hopkins ,  Srikant Jayanti

IPC: H01L27/115 ,  H01L27/11556 ,  H01L29/792 ,  H01L29/66 ,  H01L27/11582 ,  H01L29/788 ,  H01L27/11524

Abstract: Vertical memories and methods of making the same are discussed generally herein. In one embodiment, a vertical memory can include a vertical pillar extending to a source, an etch stop tier over the source, and a stack of alternating dielectric tiers and conductive tiers over the etch stop tier. The etch stop tier can comprise a blocking dielectric adjacent to the pillar. In another embodiment, the etch stop tier can comprise a blocking dielectric adjacent to the pillar, and a plurality of dielectric films horizontally extending from the blocking dielectric into the etch stop tier.

公开(公告)号：US10079235B2

公开(公告)日：2018-09-18

申请号：US15664183

申请日：2017-07-31

Applicant: Micron Technology, Inc.

Inventor： Suraj J. Mathew ,  Raghunath Singanamalla ,  Fawad Ahmed ,  Kris K. Brown ,  Vinay Nair ,  Gloria Yang ,  Fatma Arzum Simsek-Ege ,  Diem Thy N. Tran

IPC: H01L27/108 ,  G11C5/06 ,  G11C11/401

CPC classification number: H01L27/108 ,  G11C5/063 ,  G11C11/401 ,  G11C11/405 ,  H01L27/10841 ,  H01L27/10864

Abstract: Some embodiments include a memory cell having first, second and third transistors, with the second and third transistors being vertically displaced relative to one another. The memory cell has a semiconductor pillar extending along the second and third transistors, with the semiconductor pillar containing channel regions and source/drain regions of the second and third transistors. A capacitor may be electrically coupled between a source/drain region of the first transistor and a gate of the second transistor.

公开(公告)号：US20180166464A1

公开(公告)日：2018-06-14

申请号：US15893380

申请日：2018-02-09

Applicant: Micron Technology, Inc.

Inventor： Jie Sun ,  Fatma Arzum Simsek-Ege

IPC: H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L21/02 ,  H01L21/28 ,  H01L21/768

CPC classification number: H01L27/11582 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02244 ,  H01L21/02274 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/76816 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53271 ,  H01L27/115 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157

Abstract: Some embodiments include an integrated structure having a stack of alternating dielectric levels and conductive levels, vertically-stacked memory cells within the conductive levels, an insulative material over the stack and a select gate material over the insulative material. An opening extends through the select gate material, through the insulative material, and through the stack of alternating dielectric and conductive levels. A first region of the opening within the insulative material is wider along a cross-section than a second region of the opening within the select gate material, and is wider along the cross-section than a third region of the opening within the stack of alternating dielectric levels and conductive levels. Channel material is within the opening and adjacent the insulative material, the select gate material and the memory cells. Some embodiments include methods of forming vertically-stacked memory cells.

公开(公告)号：US09991273B2

公开(公告)日：2018-06-05

申请号：US15691477

申请日：2017-08-30

Applicant: Micron Technology, Inc.

Inventor： Charles H. Dennison ,  Akira Goda ,  John Hopkins ,  Fatma Arzum Simsek-Ege ,  Krishna K. Parat

IPC: H01L27/1156 ,  H01L27/11556 ,  H01L29/66 ,  H01L21/28 ,  H01L27/11578

CPC classification number: H01L27/11556 ,  H01L21/28273 ,  H01L27/11578 ,  H01L29/66666 ,  H01L29/66825 ,  H01L29/66833

Abstract: Floating gate memory cells in vertical memory. A control gate is formed between a first tier of dielectric material and a second tier of dielectric material. A floating gate is formed between the first tier of dielectric material and the second tier of dielectric material, wherein the floating gate includes a protrusion extending towards the control gate. A charge blocking structure is formed between the floating gate and the control gate, wherein at least a portion of the charge blocking structure wraps around the protrusion.

公开(公告)号：US20180061836A1

公开(公告)日：2018-03-01

申请号：US15664183

申请日：2017-07-31

Applicant: Micron Technology, Inc.

Inventor： Suraj J. Mathew ,  Raghunath Singanamalla ,  Fawad Ahmed ,  Kris K. Brown ,  Vinay Nair ,  Gloria Yang ,  Fatma Arzum Simsek-Ege ,  Diem Thy N. Tran

IPC: H01L27/108 ,  G11C5/06

CPC classification number: H01L27/108 ,  G11C5/063 ,  G11C11/401 ,  G11C11/405 ,  H01L27/10841 ,  H01L27/10864

Abstract: Some embodiments include a memory cell having first, second and third transistors, with the second and third transistors being vertically displaced relative to one another. The memory cell has a semiconductor pillar extending along the second and third transistors, with the semiconductor pillar containing channel regions and source/drain regions of the second and third transistors. A capacitor may be electrically coupled between a source/drain region of the first transistor and a gate of the second transistor.

公开(公告)号：US20170352704A1

公开(公告)日：2017-12-07

申请号：US15686389

申请日：2017-08-25

Applicant: Micron Technology, Inc.

Inventor： Fatma Arzum Simsek-Ege ,  Krishna K. Parat

IPC: H01L27/24 ,  H01L29/792 ,  H01L27/1158 ,  H01L27/11553 ,  H01L29/66 ,  H01L45/00 ,  H01L29/788

CPC classification number: H01L27/2454 ,  H01L27/11553 ,  H01L27/1158 ,  H01L27/2481 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7889 ,  H01L29/7926 ,  H01L45/1608

Abstract: Various embodiments comprise apparatuses and methods, such as a memory stack having a continuous cell pillar. In various embodiments, the apparatus includes a source material, a buffer material, a select gate drain (SGD), and a memory stack arranged between the source material and the SGD. The memory stack comprises alternating levels of conductor materials and dielectric materials. A continuous channel-fill material forms a cell pillar that is continuous from the source material to at least a level corresponding to the SGD.

公开(公告)号：US20170200737A1

公开(公告)日：2017-07-13

申请号：US15472052

申请日：2017-03-28

Applicant: Micron Technology, Inc.

Inventor： Jie Sun ,  Fatma Arzum Simsek-Ege

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/1157 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532 ,  H01L21/02 ,  H01L21/28 ,  H01L27/11524 ,  H01L23/522

CPC classification number: H01L27/11582 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02244 ,  H01L21/02274 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/76816 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53271 ,  H01L27/115 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157

Abstract: Some embodiments include an integrated structure having a stack of alternating dielectric levels and conductive levels, vertically-stacked memory cells within the conductive levels, an insulative material over the stack and a select gate material over the insulative material. An opening extends through the select gate material, through the insulative material, and through the stack of alternating dielectric and conductive levels. A first region of the opening within the insulative material is wider along a cross-section than a second region of the opening within the select gate material, and is wider along the cross-section than a third region of the opening within the stack of alternating dielectric levels and conductive levels. Channel material is within the opening and adjacent the insulative material, the select gate material and the memory cells. Some embodiments include methods of forming vertically-stacked memory cells.

公开(公告)号：US20170133392A1

公开(公告)日：2017-05-11

申请号：US15410469

申请日：2017-01-19

Applicant: Micron Technology, Inc.

Inventor： Fatma Arzum Simsek-Ege ,  John Hopkins ,  Srikant Jayanti

IPC: H01L27/11556 ,  H01L27/11524

CPC classification number: H01L27/11556 ,  H01L27/11524 ,  H01L27/11582 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7889 ,  H01L29/7926

Abstract: Vertical memories and methods of making the same are discussed generally herein. In one embodiment, a vertical memory can include a vertical pillar extending to a source, an etch stop tier over the source, and a stack of alternating dielectric tiers and conductive tiers over the etch stop tier. The etch stop tier can comprise a blocking dielectric adjacent to the pillar. In another embodiment, the etch stop tier can comprise a blocking dielectric adjacent to the pillar, and a plurality of dielectric films horizontally extending from the blocking dielectric into the etch stop tier.

公开(公告)号：US09455261B1

公开(公告)日：2016-09-27

申请号：US14796938

申请日：2015-07-10

Applicant: Micron Technology, Inc.

Inventor： Jie Sun ,  Fatma Arzum Simsek-Ege

IPC: H01L29/76 ,  H01L27/115 ,  H01L21/02 ,  H01L27/02 ,  H01L29/417 ,  H01L29/66 ,  H01L29/788 ,  H01L29/792 ,  H01L29/51

CPC classification number: H01L27/11582 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02244 ,  H01L21/02274 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/76816 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53271 ,  H01L27/115 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157

Abstract: Some embodiments include an integrated structure having a stack of alternating dielectric levels and conductive levels, vertically-stacked memory cells within the conductive levels, an insulative material over the stack and a select gate material over the insulative material. An opening extends through the select gate material, through the insulative material, and through the stack of alternating dielectric and conductive levels. A first region of the opening within the insulative material is wider along a cross-section than a second region of the opening within the select gate material, and is wider along the cross-section than a third region of the opening within the stack of alternating dielectric levels and conductive levels. Channel material is within the opening and adjacent the insulative material, the select gate material and the memory cells. Some embodiments include methods of forming vertically-stacked memory cells.

Abstract translation: 一些实施例包括具有交替介电水平和导电水平的叠层，导电水平内的垂直堆叠的存储单元，堆叠上的绝缘材料和绝缘材料上的选择栅极材料的集成结构。 开口延伸穿过选择栅材料，穿过绝缘材料，并通过交替的电介质层和导电层叠。 绝缘材料内的开口的第一区域沿着选择栅极材料内的开口的第二区域的横截面较宽，并且沿着横截面比在交替堆叠内的开口的第三区域更宽 介电水平和导电水平。 通道材料在开口内并且与绝缘材料，选择栅极材料和存储单元相邻。 一些实施例包括形成垂直堆叠的存储器单元的方法。