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    IDLE MODE TEMPERATURE CONTROL FOR MEMORY SYSTEMS
    31.
    发明申请
    IDLE MODE TEMPERATURE CONTROL FOR MEMORY SYSTEMS 有权

    公开(公告)号：US20240419353A1

    公开(公告)日：2024-12-19

    申请号：US18750250

    申请日：2024-06-21

    Applicant: Micron Technology, Inc.

    Inventor： Francesco Basso ,  Antonino Pollio ,  Francesco Falanga ,  Massimo Iaculo

    IPC: G06F3/06

    Abstract: Methods, systems, and devices for idle mode temperature control for memory systems are described. A memory system may implement the use of one or more dummy access commands to reduce the effects of errors introduced by temperature changes while the memory system is in an idle mode. For example, performing one or more access commands, such as one or more read commands, may increase a temperature of a memory device and support a desired operating temperature for the memory device while the memory system is in the idle mode. The memory system may measure the temperature of the memory device during the idle mode. If the memory system determines that the temperature of the memory device has fallen below a threshold temperature, the memory system may issue a quantity of dummy access commands to the memory device, and the corresponding dummy access operations may result in a temperature increase at the memory device.

    FIRMWARE VERIFICATION USING PARITY INFORMATION
    32.
    发明申请
    FIRMWARE VERIFICATION USING PARITY INFORMATION 有权

    公开(公告)号：US20240394371A1

    公开(公告)日：2024-11-28

    申请号：US18669487

    申请日：2024-05-20

    Applicant: Micron Technology, Inc.

    Inventor： Flavio Pace ,  Antonino Pollio ,  Laura Ferrante

    IPC: G06F21/57 ,  H04L9/32

    Abstract: Methods, systems, and apparatuses include reading a firmware image from a memory device. Parity data for the firmware image is computed. A first authentication code associated with the firmware image is received. A second authentication code is computed by performing a cryptographic operation on the parity data. It is determined that the first authentication code and the second authentication code match. The firmware image is loaded onto the memory device in response to determining that the first authentication code and the second authentication code match.

    Split cache for address mapping data
    33.
    发明授权
    Split cache for address mapping data 有权

    公开(公告)号：US12007897B2

    公开(公告)日：2024-06-11

    申请号：US17886112

    申请日：2022-08-11

    Applicant: Micron Technology, Inc.

    Inventor： Nicola Colella ,  Antonino Pollio

    IPC: G06F12/0846 ,  G06F12/02 ,  G06F12/0804 ,  G06F12/0891

    CPC classification number: G06F12/0848 ,  G06F12/0246 ,  G06F12/0804 ,  G06F12/0891 ,  G06F2212/7201

    Abstract: Methods, systems, and devices for a split cache for address mapping data are described. A memory system may include a cache (e.g., including a first and second portion) for storing data that indicates a mapping between logical addresses associated with a host system and physical addresses of the memory system. The memory system may store data (e.g., the address mapping data) within the first portion of the cache. Additionally, the memory system may store an indication of whether the data is used for any access operations during a duration that the data is stored in the first portion of the cache. The memory system may transfer subsets of the data to the second portion of the cache if they are used for access operations during the duration.

    IDLE MODE TEMPERATURE CONTROL FOR MEMORY SYSTEMS
    34.
    发明公开
    IDLE MODE TEMPERATURE CONTROL FOR MEMORY SYSTEMS 审中-公开

    公开(公告)号：US20240069784A1

    公开(公告)日：2024-02-29

    申请号：US17900361

    申请日：2022-08-31

    Applicant: Micron Technology, Inc.

    Inventor： Francesco Basso ,  Antonino Pollio ,  Francesco Falanga ,  Massimo Iaculo

    IPC: G06F3/06

    CPC classification number: G06F3/0653 ,  G06F3/0604 ,  G06F3/0652 ,  G06F3/0679

    Abstract: Methods, systems, and devices for idle mode temperature control for memory systems are described. A memory system may implement the use of one or more dummy access commands to reduce the effects of errors introduced by temperature changes while the memory system is in an idle mode. For example, performing one or more access commands, such as one or more read commands, may increase a temperature of a memory device and support a desired operating temperature for the memory device while the memory system is in the idle mode. The memory system may measure the temperature of the memory device during the idle mode. If the memory system determines that the temperature of the memory device has fallen below a threshold temperature, the memory system may issue a quantity of dummy access commands to the memory device, and the corresponding dummy access operations may result in a temperature increase at the memory device.

    DYNAMIC UPDATES TO LOGICAL-TO-PHYSICAL ADDRESS TRANSLATION TABLE BITMAPS
    35.
    发明公开
    DYNAMIC UPDATES TO LOGICAL-TO-PHYSICAL ADDRESS TRANSLATION TABLE BITMAPS 审中-公开

    公开(公告)号：US20240061787A1

    公开(公告)日：2024-02-22

    申请号：US17890507

    申请日：2022-08-18

    Applicant: Micron Technology, Inc.

    Inventor： Nicola Colella ,  Antonino Pollio ,  Gianfranco Ferrante

    IPC: G06F12/1009 ,  G06F12/02 ,  G06F12/0873

    CPC classification number: G06F12/1009 ,  G06F12/0246 ,  G06F12/0873

    Abstract: A method includes: creating L2P tables while programming virtual blocks (VBs) across memory planes; creating an L2P bitmap for each VB, the L2P bitmap identifying logical addresses, within each L2P table, that belong to each VB; creating a VB bitmap for each L2P table, the VB bitmap identifying virtual blocks to which the respective L2P table points; creating an updated VB bitmap for a first L2P table based on changes to the first L2P table; determining that an entry in the VB bitmap is different than the entry in the updated VB bitmap, the entry corresponding to a particular VB; identifying an L2P bitmap corresponding to the particular VB; changing a bit within the identified L2P bitmap for an L2P mapping corresponding to the entry; and employing the identified L2P bitmap to determine L2P table(s) of the respective L2P tables that contain valid logical addresses for the particular VB.

    TECHNIQUES FOR PAGE LINE FILLER DATA
    36.
    发明公开
    TECHNIQUES FOR PAGE LINE FILLER DATA 审中-公开

    公开(公告)号：US20230244414A1

    公开(公告)日：2023-08-03

    申请号：US18095771

    申请日：2023-01-11

    Applicant: Micron Technology, Inc.

    Inventor： Nicola Colella ,  Antonino Pollio ,  Gianfranco Ferrante

    IPC: G06F3/06 ,  G06F12/02

    CPC classification number: G06F3/0656 ,  G06F12/0253 ,  G06F3/0604 ,  G06F3/0676 ,  G06F3/0679

    Abstract: Methods, systems, and devices for using page line filler data are described. In some examples, a memory system may store data within a write buffer of the memory system. The memory system may initiate an operation to transfer the write buffer data to a memory device, for example, due to a command to perform a memory management operation (e.g., cache synchronization, context switching, or the like) from a host system. In some examples, a quantity of write buffer data may fail to satisfy a data size threshold. Thus, the memory system may aggregate the data in the write buffer with valid data from a block of the memory device associated with garbage collection. The memory system may aggregate the write buffer data with the garbage collection data until the aggregated data satisfies the data size threshold. The memory system may then write the aggregated data to the memory device.

    TECHNIQUES FOR PAGE LINE FILLER DATA
    37.
    发明申请
    TECHNIQUES FOR PAGE LINE FILLER DATA 有权

    公开(公告)号：US20220374163A1

    公开(公告)日：2022-11-24

    申请号：US17323974

    申请日：2021-05-18

    Applicant: Micron Technology, Inc.

    Inventor： Nicola Colella ,  Antonino Pollio ,  Gianfranco Ferrante

    IPC: G06F3/06 ,  G06F12/02

    Abstract: Methods, systems, and devices for using page line filler data are described. In some examples, a memory system may store data within a write buffer of the memory system. The memory system may initiate an operation to transfer the write buffer data to a memory device, for example, due to a command to perform a memory management operation (e.g., cache synchronization, context switching, or the like) from a host system. In some examples, a quantity of write buffer data may fail to satisfy a data size threshold. Thus, the memory system may aggregate the data in the write buffer with valid data from a block of the memory device associated with garbage collection. The memory system may aggregate the write buffer data with the garbage collection data until the aggregated data satisfies the data size threshold. The memory system may then write the aggregated data to the memory device.

    INITIALIZATION TECHNIQUES FOR MEMORY DEVICES
    38.
    发明申请
    INITIALIZATION TECHNIQUES FOR MEMORY DEVICES 有权

    公开(公告)号：US20220223211A1

    公开(公告)日：2022-07-14

    申请号：US17586526

    申请日：2022-01-27

    Applicant: Micron Technology, Inc.

    Inventor： Antonino Pollio ,  Giuseppe Vito Portacci ,  Mauro Luigi Sali ,  Alessandro Magnavacca

    IPC: G11C16/20 ,  G11C16/16 ,  G11C29/42 ,  G11C29/14 ,  G11C16/26

    Abstract: Methods, systems, and devices for initialization techniques for memory devices are described. A memory system may include a memory array on a first die and a controller on a second die, where the second die is coupled with the first die. The controller may perform an initialization procedure based on operating instructions stored within the memory system. For example, the controller may read a first set of operating instructions from read-only memory on the second die. The controller may obtain a second set of operating instructions stored at a memory block of the memory array on the first die, with the memory block indicated by the first set of operating instructions. The controller may complete or at least further the initialization procedure based on the second set of operating instructions.

    ENHANCEMENT FOR ACTIVATION AND DEACTIVATION OF MEMORY ADDRESS REGIONS
    39.
    发明申请
    ENHANCEMENT FOR ACTIVATION AND DEACTIVATION OF MEMORY ADDRESS REGIONS 有权

    公开(公告)号：US20220156185A1

    公开(公告)日：2022-05-19

    申请号：US16952813

    申请日：2020-11-19

    Applicant: Micron Technology, Inc.

    Inventor： Nicola Colella ,  Antonino Pollio ,  Hua Tan

    IPC: G06F12/0802 ,  G06F12/02

    Abstract: Methods, systems, and devices for read operations for regions of a memory device are described. In some examples, a memory device may include a first cache for storing mappings between logical addresses and physical addresses of the memory device, and a second cache for storing indices associated with entries removed from the first cache. The memory device may include a controller configured to load mappings to the first cache upon receiving read commands. When the first cache is full, and when the memory device receives a read command, the controller may remove an entry from the first cache and may store an index associated with the removed entry to the second cache. The controller may then transmit a mapping associated with the index to a host device for use in a HPB operation.

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