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    Apparatuses and methods for memory operations having variable latencies
    31.
    发明授权
    Apparatuses and methods for memory operations having variable latencies 有权

    公开(公告)号：US09754648B2

    公开(公告)日：2017-09-05

    申请号：US13794471

    申请日：2013-03-11

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Graziano Mirichigni ,  Corrado Villa ,  Luca Porzio

    IPC: G11C7/10 ,  G11C7/22 ,  G06F13/16

    CPC classification number: G11C7/22 ,  G06F13/1689 ,  G11C7/1063

    Abstract: Apparatuses and methods for performing memory operations are described. In an example apparatus, a memory is configured to receive a memory instruction and perform a memory operation responsive to the memory instruction. The memory is further configured to provide an acknowledgement indicative of an end of the variable latency period wherein the acknowledgement includes information related to an acceptance of a memory instruction. Data associated with the memory instruction is exchanged with the memory following the acknowledgement. In an example method a read instruction and an address from which read data is to be read is received. A write operation is suspended responsive to the read instruction and an acknowledgement indicative of an end of the variable latency period is provided. Read data for the read instruction is provided and the write operation is continued to be suspended for a hold-off period following completion of the read operation.

    ERROR CORRECTION CODE FOR UNIDIRECTIONAL MEMORY
    34.
    发明申请
    ERROR CORRECTION CODE FOR UNIDIRECTIONAL MEMORY 有权
    非法存储器的错误校正码

    公开(公告)号：US20130283121A1

    公开(公告)日：2013-10-24

    申请号：US13846538

    申请日：2013-03-18

    Applicant: Micron Technology, Inc.

    Inventor： Christophe Laurent ,  Paolo Amato ,  Marco Sforzin ,  Corrado Villa

    IPC: H03M13/29

    CPC classification number: G06F11/1068 ,  G11C29/52 ,  H03M13/2909

    Abstract: A memory array and a method of writing to a unidirectional non-volatile storage cell are disclosed whereby a user data word is transformed to an internal data word and written to one or more unidirectional data storage cells according to a cell coding scheme. A check word may be generated that corresponds to the internal data word. In some embodiments, the check word may be generated by inverting one or more bits of an intermediate check word. Other embodiments may be described and claimed.

    Abstract translation: 公开了一种写入单向非易失性存储单元的存储器阵列和方法，其中用户数据字被转换为内部数据字，并根据小区编码方案写入一个或多个单向数据存储单元。 可以生成对应于内部数据字的检查字。 在一些实施例中，可以通过反转中间检查字的一个或多个位来产生检验字。 可以描述和要求保护其他实施例。

    VARIABLE PAGE SIZE ARCHITECTURE
    35.
    发明公开
    VARIABLE PAGE SIZE ARCHITECTURE 审中-公开

    公开(公告)号：US20240347088A1

    公开(公告)日：2024-10-17

    申请号：US18617019

    申请日：2024-03-26

    Applicant: Micron Technology, Inc.

    Inventor： Corrado Villa

    IPC: G11C8/16 ,  G11C7/04 ,  G11C7/10 ,  G11C8/10 ,  G11C29/18

    CPC classification number: G11C8/16 ,  G11C7/04 ,  G11C7/1012 ,  G11C7/1045 ,  G11C8/10 ,  G11C2029/1804 ,  G11C2207/2245

    Abstract: Methods, systems, and devices for operating a memory array with variable page sizes are described. The page size may be dynamically changed, and multiple rows of the memory array may be accessed in parallel to create the desired page size. A memory bank of the array may contain multiple memory sections, and each memory section may have its own set of sense components (e.g., sense amplifiers) to read or program the memory cells. Multiple memory sections may thus be accessed in parallel to create a memory page from multiple rows of memory cells. The addressing scheme may be modified based on the page size. The logic row address may identify the memory sections to be accessed in parallel. The memory sections may also be linked and accessing a row in one section may automatically access a row in a second memory section.

    Voltage equalization for pillars of a memory array
    36.
    发明授权
    Voltage equalization for pillars of a memory array 有权

    公开(公告)号：US11735255B2

    公开(公告)日：2023-08-22

    申请号：US17880804

    申请日：2022-08-04

    Applicant: Micron Technology, Inc.

    Inventor： Corrado Villa ,  Ferdinando Bedeschi ,  Paolo Fantini

    IPC: G11C13/00 ,  H10N70/00 ,  H10N70/20

    CPC classification number: G11C13/0026 ,  G11C13/00 ,  G11C13/003 ,  G11C13/0004 ,  H10N70/066 ,  H10N70/231 ,  H10N70/882

    Abstract: Methods, systems, and devices for voltage equalization for pillars of a memory array are described. In some examples, a memory array may be configured with conductive pillars that are each coupled with a respective set of memory cells, and may be selectively coupled with an access line. To support a dissipation or equalization of charge from unselected pillars, the memory array may be configured with a material layer or level that provides a dissipative coupling, such as a coupling having a relatively high resistance or a degree of capacitance, with a ground voltage or other voltage source (e.g., to support a passive equalization). Additionally, or alternatively, a memory array may be configured to support an active dissipation of accumulated charge or voltage by selectively coupling pillars that have been operated in a floating condition with a ground voltage or other voltage source (e.g., to perform a dynamic equalization).

    Systems and methods for adaptive self-referenced reads of memory devices
    37.
    发明授权
    Systems and methods for adaptive self-referenced reads of memory devices 有权

    公开(公告)号：US11538522B1

    公开(公告)日：2022-12-27

    申请号：US17364067

    申请日：2021-06-30

    Applicant: Micron Technology, Inc.

    Inventor： Graziano Mirichigni ,  Corrado Villa

    IPC: G11C7/14 ,  G11C16/28 ,  G11C13/00

    Abstract: Methods and systems include memory devices with a memory array comprising a plurality of memory cells. The memory devices include a control circuit operatively coupled to the memory array and configured to receive a read request for data and to apply a first voltage to the memory array based on the read request. The control circuit is additionally configured to count a total number of the plurality of memory cells that have switched to an active read state based on the first voltage and to apply a second voltage to the memory array based on the total number. The control circuit is further configured to return the data based at least on bits stored in a first and a second set of the plurality of memory cells.

    Wordline capacitance balancing
    38.
    发明授权
    Wordline capacitance balancing 有权

    公开(公告)号：US11462289B2

    公开(公告)日：2022-10-04

    申请号：US17236729

    申请日：2021-04-21

    Applicant: Micron Technology, Inc.

    Inventor： Corrado Villa ,  Shane D. Moser

    IPC: G11C29/18 ,  G11C11/419 ,  G11C11/408 ,  G11C11/22 ,  G11C13/00 ,  G11C16/04

    Abstract: Methods, systems, and devices for word line capacitance balancing are described. A memory device may include a set of memory tiles, where one or more memory tiles may be located at a boundary of the set. Each boundary memory tile may have a word line coupled with a driver and a subarray of memory cells, and may also include a load balancing component (e.g., a capacitive component) coupled with the driver. In some examples, the load balancing component may be coupled with an output line of the driver (such as a word line) or an input of the driver (such as a line providing a source signal). The load balancing component may adapt a load output from the driver to the subarray of memory cells such that the load of the memory tile at the boundary may be similar to the load of other memory tiles not at the boundary.

    VOLTAGE EQUALIZATION FOR PILLARS OF A MEMORY ARRAY
    39.
    发明申请
    VOLTAGE EQUALIZATION FOR PILLARS OF A MEMORY ARRAY 有权

    公开(公告)号：US20220180926A1

    公开(公告)日：2022-06-09

    申请号：US17116893

    申请日：2020-12-09

    Applicant: Micron Technology, Inc.

    Inventor： Corrado Villa ,  Ferdinando Bedeschi ,  Paolo Fantini

    IPC: G11C13/00 ,  H01L45/00

    Abstract: Methods, systems, and devices for voltage equalization for pillars of a memory array are described. In some examples, a memory array may be configured with conductive pillars that are each coupled with a respective set of memory cells, and may be selectively coupled with an access line. To support a dissipation or equalization of charge from unselected pillars, the memory array may be configured with a material layer or level that provides a dissipative coupling, such as a coupling having a relatively high resistance or a degree of capacitance, with a ground voltage or other voltage source (e.g., to support a passive equalization). Additionally or alternatively, a memory array may be configured to support an active dissipation of accumulated charge or voltage by selectively coupling pillars that have been operated in a floating condition with a ground voltage or other voltage source (e.g., to perform a dynamic equalization).

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