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    Memory devices with distributed block select for a vertical string driver tile architecture
    31.
    发明授权
    Memory devices with distributed block select for a vertical string driver tile architecture 有权

    公开(公告)号：US11217310B2

    公开(公告)日：2022-01-04

    申请号：US16862380

    申请日：2020-04-29

    Applicant: Micron Technology, Inc.

    Inventor： Eric N. Lee

    IPC: G11C16/08 ,  G11C16/04 ,  G11C5/02 ,  G11C8/08 ,  G11C8/12

    Abstract: Memory devices are disclosed. A memory device may include multiple pairs of tiles. At least some of the pairs of tiles may include a block select circuit. At least one portion of the block select circuit within a first pair of tiles of the multiple pairs of tiles is offset from at least one other portion of the block select circuit within a second pair of tiles of the multiple pairs of tiles. Also, at least one pair of tiles of the multiple pair of tiles may include an associated vertical string driver offset from each of a first tile and a second tile of an associated pair of tiles.

    MEMORY DEVICES WITH DISTRIBUTED BLOCK SELECT FOR A VERTICAL STRING DRIVER TILE ARCHITECTURE
    32.
    发明申请
    MEMORY DEVICES WITH DISTRIBUTED BLOCK SELECT FOR A VERTICAL STRING DRIVER TILE ARCHITECTURE 审中-公开

    公开(公告)号：US20190304542A1

    公开(公告)日：2019-10-03

    申请号：US16446234

    申请日：2019-06-19

    Applicant: Micron Technology, Inc.

    Inventor： Eric N. Lee

    IPC: G11C16/08 ,  G11C16/04 ,  G11C8/08 ,  G11C8/12 ,  G11C5/02

    Abstract: Memory device having a tile architecture are disclosed. The memory device may include a first plane having multiple pairs of tiles, wherein at least some of the pairs of tiles of the first plane include a distributed block select circuit and page buffer circuitry. Another memory device may include a memory array, and a CMOS under array region. At least some tile regions may include portions of a total amount of block select circuitry distributed throughout the CUA region, vertical string drivers located outside of the memory array, and page buffer circuitry coupled with the memory array. Another memory device may include a first tile pair including a first tile, a second tile, a first vertical string driver therebetween, a first page buffer region that is greater than 50% of area for the first tile pair, and a first portion of a distributed block select circuitry.

    Wave pipeline
    33.
    发明授权
    Wave pipeline 有权

    公开(公告)号：US10360956B2

    公开(公告)日：2019-07-23

    申请号：US15834279

    申请日：2017-12-07

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Kaveh Shakeri ,  Ali Feiz Zarrin Ghalam ,  Qiang Tang ,  Eric N. Lee

    IPC: G11C7/10 ,  G11C7/22 ,  G11C7/06 ,  G11C8/06 ,  G11C8/04 ,  G11C8/18 ,  G11C16/04

    Abstract: A wave pipeline includes a first stage, a plurality of second stages, and a third stage. The first stage receives a data signal representative of data and a clock signal, and may process the data at a first data rate equal to a clock rate of the clock signal. Each second stage may process respective data in response to a respective clock cycle received from the first stage at a second data rate equal to the first data rate times the number of second stages. The third stage may process data received from each second stage at the first data rate. The first stage divides the data signal and the clock signal between the plurality of second stages. The third stage merges the respective data and the respective clock cycles from each of the plurality of second stages to provide a merged data signal and a return clock signal.

    SEMICONDUCTOR DEVICE STRUCTURES INCLUDING STAIRCASE STRUCTURES, AND RELATED METHODS
    35.
    发明申请
    SEMICONDUCTOR DEVICE STRUCTURES INCLUDING STAIRCASE STRUCTURES, AND RELATED METHODS 审中-公开

    公开(公告)号：US20190139977A1

    公开(公告)日：2019-05-09

    申请号：US16202999

    申请日：2018-11-28

    Applicant: Micron Technology, Inc.

    Inventor： Eric N. Lee

    IPC: H01L27/11575 ,  H01L23/528 ,  H01L27/11573 ,  H01L27/11526 ,  H01L27/11548 ,  H01L27/1157 ,  H01L27/11556 ,  H01L27/11524 ,  H01L27/11582 ,  H01L21/764

    Abstract: A semiconductor device structure comprises stacked tiers each comprising at least one conductive structure and at least one insulating structure longitudinally adjacent the at least one conductive structure, at least one staircase structure having steps comprising lateral ends of the stacked tiers, and at least one opening extending through the stacked tiers and continuously across an entire length of the at least one staircase structure. The at least one conductive structure of each of the stacked tiers extends continuously from at least one of the steps of the at least one staircase structure and around the at least one opening to form at least one continuous conductive path extending completely across each of the stacked tiers. Additional semiconductor device structures, methods of forming semiconductor device structures, and electronic systems are also described.

    APPARATUSES AND METHODS FOR A MEMORY DIE ARCHITECTURE
    37.
    发明申请
    APPARATUSES AND METHODS FOR A MEMORY DIE ARCHITECTURE 有权
    记忆体建筑的装置和方法

    公开(公告)号：US20140258619A1

    公开(公告)日：2014-09-11

    申请号：US13793347

    申请日：2013-03-11

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Dean K. Nobunaga ,  Ali Feiz Zarrin Ghalam ,  Xiaojiang Guo ,  Eric N. Lee

    IPC: G06F12/08

    CPC classification number: G06F3/0629 ,  G06F3/0604 ,  G06F3/061 ,  G06F3/0683 ,  G06F12/0802 ,  G06F12/0893 ,  G06F13/1684 ,  G06F13/4068 ,  G06F2212/1016 ,  G06F2212/3042 ,  G11C5/066 ,  G11C7/1048 ,  G11C8/12 ,  G11C11/00

    Abstract: Apparatuses and methods for reducing capacitance on a data bus are disclosed herein. In accordance with one or more described embodiments, an apparatus may comprise a plurality of memories coupled to an internal data bus and a command and address bus, each of the memories configured to receive a command on the command and address bus. One of the plurality of memories may be coupled to an external data bus. The one of the plurality of memories may be configured to provide program data to the internal data bus when the command comprises a program command and another of the plurality of memories is a target memory of the program command and may be configured to provide read data to the external data bus when the command comprises a read command and the another of the plurality of memories is a target memory of the read command.

    Abstract translation: 本文公开了用于减小数据总线上的电容的装置和方法。 根据一个或多个所描述的实施例，装置可以包括耦合到内部数据总线和命令和地址总线的多个存储器，每个存储器被配置为在命令和地址总线上接收命令。 多个存储器中的一个可以耦合到外部数据总线。 多个存储器中的一个可以被配置为当命令包括程序命令时向内部数据总线提供程序数据，并且多个存储器中的另一个是程序命令的目标存储器，并且可以被配置为将读取数据提供给 当命令包括读取命令并且多个存储器中的另一个是读取命令的目标存储器时的外部数据总线。

    DATA BURST SUSPEND MODE USING PAUSE DETECTION
    39.
    发明申请
    DATA BURST SUSPEND MODE USING PAUSE DETECTION 有权

    公开(公告)号：US20250077455A1

    公开(公告)日：2025-03-06

    申请号：US18951879

    申请日：2024-11-19

    Applicant: Micron Technology, Inc.

    Inventor： Eric N. Lee ,  Leonid Minz ,  Yoav Weinberg ,  Ali Feiz Zarrin Ghalam ,  Luigi Pilolli

    IPC: G06F13/30 ,  G06F13/16

    Abstract: Operations include determining, based on a period of time during which a logical level of the signal line is maintained at a first logical level, that a data transfer to the memory array is being suspended, determining, while the data transfer is suspended, whether the logical level of the signal line has changed from the first logical level to a second logical level, and in response to determining that the logical level of the signal line has changed from the first logical level to the second logical level, causing warm-up cycles to be performed.

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