公开(公告)号：US20220066679A1

公开(公告)日：2022-03-03

申请号：US17004135

申请日：2020-08-27

Applicant: Micron Technology, Inc.

Inventor： Adam J. Hieb ,  Adam C. Guy ,  Sanjay Tiwari ,  Todd A. Marquart

IPC: G06F3/06 ,  G06F11/07

Abstract: A system includes a memory device and a processing device coupled to the memory device. The memory processing device can perform operations including receiving data indicative of occurrence of a plurality of events. The processing device can perform operations including determining an event log type for each of the plurality of events. The processing device can perform operations including storing an identifier associated with each of the determined event log types. The processing device can perform operations including updating a counter value associated with each identifier in response to occurrence of an event associated with the respective identifier.

公开(公告)号：US20180301173A1

公开(公告)日：2018-10-18

申请号：US15489342

申请日：2017-04-17

Applicant: Micron Technology, Inc.

Inventor： Sanjay Tiwari

IPC: G11C7/06

CPC classification number: G11C7/062 ,  G11C7/065 ,  G11C7/1006 ,  G11C7/1012 ,  G11C11/4091 ,  G11C11/4096

Abstract: The present disclosure includes apparatuses and methods related to performing a greater vector determination in memory. An example apparatus comprises a first group of memory cells coupled to a sense line and to a number of first access lines and a second group of memory cells coupled to the sense line and to a number of second access lines. The example apparatus comprises a controller configured to operate sensing circuitry to compare a value of a first element stored in the first group of memory cells to a value of a second element stored in the second group of memory cells to determine which of the value of the first element and the value of the second element is greater.

公开(公告)号：US20180173499A1

公开(公告)日：2018-06-21

申请号：US15898894

申请日：2018-02-19

Applicant: Micron Technology, Inc.

Inventor： Sanjay Tiwari

IPC: G06F7/523 ,  G11C7/10 ,  G11C11/4096

CPC classification number: G06F7/523 ,  G06F2207/4802 ,  G11C7/1006 ,  G11C11/4096

Abstract: Examples of the present disclosure provide apparatuses and methods for performing multiplication operations in a memory. An example method comprises performing a multiplication operation on a first element stored in a group of memory cells coupled to a first access line and a number of sense lines of a memory array and a second element stored in a group of memory cells coupled to a second access line and the number of sense lines of the memory array. The method can include a number operations performed without transferring data via an input/output (I/O) line.

公开(公告)号：US20170365310A1

公开(公告)日：2017-12-21

申请号：US15692959

申请日：2017-08-31

Applicant: Micron Technology, Inc.

Inventor： Sanjay Tiwari

IPC: G11C7/22 ,  G11C7/12 ,  G11C7/10 ,  G11C8/10 ,  G11C7/06

CPC classification number: G11C7/22 ,  G11C7/065 ,  G11C7/1006 ,  G11C7/1012 ,  G11C7/106 ,  G11C7/12 ,  G11C8/10

Abstract: The present disclosure includes apparatuses and methods related to performing comparison operations in memory. An example apparatus can include a first group of memory cells coupled to a first access line and configured to store a plurality of first elements, and a second group of memory cells coupled to a second access line and configured to store a plurality of second elements. The apparatus can include a controller configured to cause the plurality of first elements to be compared with the plurality of second elements by controlling sensing circuitry to perform a number of operations without transferring data via an input/output (I/O) line, and the plurality of first elements and the plurality of second elements can be compared in parallel.

公开(公告)号：US20170365304A1

公开(公告)日：2017-12-21

申请号：US15692783

申请日：2017-08-31

Applicant: Micron Technology, Inc.

Inventor： Jason T. Zawodny ,  Sanjay Tiwari ,  Richard C. Murphy

IPC: G11C7/10 ,  G11C5/06

CPC classification number: G11C7/1012 ,  G11C5/06 ,  G11C5/066 ,  G11C7/1006 ,  G11C11/4091

Abstract: Examples of the present disclosure provide apparatuses and methods for storing a first element in memory cells coupled to a first sense line and a plurality of access line. The examples can include storing a second element in memory cells coupled to a second sense line and the plurality of access lines. The memory cells coupled to the first sense line can be separated from the memory cells coupled to the second sense line by at least memory cells coupled to a third sense line and the plurality of access lines. The examples can include storing the second element in the memory cells coupled to the third sense line.

公开(公告)号：US20170309316A1

公开(公告)日：2017-10-26

申请号：US15591899

申请日：2017-05-10

Applicant: Micron Technology, Inc.

Inventor： Jason T. Zawodny ,  Sanjay Tiwari

IPC: G11C7/10 ,  G11C7/06 ,  G06F13/16 ,  G06F3/06 ,  G11C7/22

CPC classification number: G11C7/1012 ,  G06F3/0619 ,  G06F3/065 ,  G06F3/0685 ,  G06F13/1663 ,  G11C7/065 ,  G11C7/10 ,  G11C7/1006 ,  G11C7/1036 ,  G11C7/22 ,  G11C16/10 ,  G11C16/24 ,  G11C16/26 ,  G11C2207/005 ,  G11C2211/5641

Abstract: The present disclosure includes apparatuses and methods related to performing corner turn operations using sensing circuitry. An example apparatus comprises a first group of memory cells coupled to an access line and a plurality of sense lines and a second group of memory cells coupled to a plurality of access lines and a sense line. The example apparatus comprises a controller configured to cause a corner turn operation using sensing circuitry on an element stored in the first group of memory cells resulting in the element being stored in the second group of memory cells.

公开(公告)号：US20170309314A1

公开(公告)日：2017-10-26

申请号：US15133986

申请日：2016-04-20

Applicant: Micron Technology, Inc.

Inventor： Jason T. Zawodny ,  Sanjay Tiwari

IPC: G11C7/06 ,  G11C8/16 ,  G11C8/10

CPC classification number: G11C7/065 ,  G11C8/10 ,  G11C8/16 ,  G11C15/043

Abstract: The present disclosure includes apparatuses and methods related to performing corner turn operations using sensing circuitry. An example apparatus comprises a first group of memory cells coupled to an access line and a plurality of sense lines and a second group of memory cells coupled to a plurality of access lines and one of the plurality of sense lines. The access line can be a same access line as one of the plurality of access lines. The example apparatus comprises a controller configured to cause a corner turn operation on an element stored in the first group of memory cells resulting in the element being stored in the second group of memory cells to be performed using sensing circuitry.

公开(公告)号：US20170293434A1

公开(公告)日：2017-10-12

申请号：US15093448

申请日：2016-04-07

Applicant: Micron Technology, Inc.

Inventor： Sanjay Tiwari

IPC: G06F3/06 ,  G11C7/06

Abstract: Examples of the present disclosure provide apparatuses and methods for span mask generation. An example method comprises creating, using sensing circuitry, a number of bit vectors, wherein each of the number of bit vectors includes a repeating pattern based on a size of the number of bit vectors and a particular mask depth.

公开(公告)号：US09747961B2

公开(公告)日：2017-08-29

申请号：US14836673

申请日：2015-08-26

Applicant: Micron Technology, Inc.

Inventor： Sanjay Tiwari

IPC: G11C7/10 ,  G06F12/02 ,  G06F9/302 ,  G06F9/30

CPC classification number: G11C7/10 ,  G06F7/00 ,  G06F7/535 ,  G06F9/3001 ,  G06F12/02 ,  G06F12/0207 ,  G11C7/1006

Abstract: Examples of the present disclosure provide apparatuses and methods related to performing division operations in memory. An example apparatus might include a first group of memory cells coupled to a first access line and configured to store a dividend element. An example apparatus might include a second group of memory cells coupled to a second access line and configured to store a divisor element. An example apparatus might also include a controller configured to cause the dividend element to be divided by the divisor element by controlling sensing circuitry to perform a number of operations without transferring data via an input/output (I/O) line.

公开(公告)号：US09741399B2

公开(公告)日：2017-08-22

申请号：US15060222

申请日：2016-03-03

Applicant: Micron Technology, Inc.

Inventor： Sanjay Tiwari

IPC: G11C7/10 ,  G11C7/06 ,  G11C11/4091 ,  G11C11/4096

CPC classification number: G11C7/1036 ,  G11C7/065 ,  G11C7/1006 ,  G11C7/1012 ,  G11C11/4091 ,  G11C11/4096

Abstract: Examples of the present disclosure provide apparatuses and methods for performing shift operations in a memory. An example method comprises performing a shift operation a first element stored in a first group of memory cells coupled to a first access line and a number of sense lines of a memory array and a second element stored in a second group of memory cells coupled to a second access line and the number of sense lines of the memory array. The method can include shifting the first element by a number of bit positions defined by the second element by performing a number of AND operations, OR operations, SHIFT operations, and INVERT operations performed without transferring data via an input/output (I/O) line.