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    PRIORITIZED SECURITY
    32.
    发明申请
    PRIORITIZED SECURITY 审中-公开

    公开(公告)号：US20190065085A1

    公开(公告)日：2019-02-28

    申请号：US15692299

    申请日：2017-08-31

    Applicant: Micron Technology, Inc.

    Inventor： Sebastien Andre Jean

    IPC: G06F3/06 ,  G06F12/02

    Abstract: Disclosed in some examples are systems, methods, memory devices, and machine readable mediums for a fast secure data destruction for NAND memory devices that renders data in a memory cell unreadable. Instead of going through all the erase phases, the memory device may remove sensitive data by performing only the pre-programming phase of the erase process. Thus, the NAND doesn't perform the second and third phases of the erase process. This is much faster and results in data that cannot be reconstructed. In some examples, because the erase pulse is not actually applied and because this is simply a programming operation, data may be rendered unreadable at a per-page level rather than a per-block level as in traditional erases.

    MANAGED NVM ADAPTIVE CACHE MANAGEMENT
    36.
    发明申请
    MANAGED NVM ADAPTIVE CACHE MANAGEMENT 有权

    公开(公告)号：US20220357863A1

    公开(公告)日：2022-11-10

    申请号：US17870320

    申请日：2022-07-21

    Applicant: Micron Technology, Inc.

    Inventor： Carla L. Christensen ,  Jianmin Huang ,  Sebastien Andre Jean ,  Kulachet Tanpairoj

    IPC: G06F3/06 ,  G06F12/0893 ,  G06F12/02

    Abstract: Disclosed in some examples are memory devices which feature customizable Single Level Cell (SLC) and Multiple Level Cell (MLC) configurations. The configuration (e.g., the size and position) of the SLC cache may have an impact on power consumption, speed, and other performance of the memory device. An operating system of an electronic device to which the memory device is installed may wish to achieve different performance of the device based upon certain conditions detectable by the operating system. In this way, the performance of the memory device can be customized by the operating system through adjustments of the performance characteristics of the SLC cache.

    PRIORITIZED SECURITY
    37.
    发明申请
    PRIORITIZED SECURITY 有权

    公开(公告)号：US20220113880A1

    公开(公告)日：2022-04-14

    申请号：US17558224

    申请日：2021-12-21

    Applicant: Micron Technology, Inc.

    Inventor： Sebastien Andre Jean

    IPC: G06F3/06 ,  G06F12/02 ,  G06F21/79

    Abstract: Disclosed in some examples are systems, methods, memory devices, and machine readable mediums for a fast secure data destruction for NAND memory devices that renders data in a memory cell unreadable. Instead of going through all the erase phases, the memory device may remove sensitive data by performing only the pre-programming phase of the erase process. Thus, the NAND doesn't perform the second and third phases of the erase process. This is much faster and results in data that cannot be reconstructed. In some examples, because the erase pulse is not actually applied and because this is simply a programming operation, data may be rendered unreadable at a per-page level rather than a per-block level as in traditional erases.

    Managed NAND data compression
    38.
    发明授权
    Managed NAND data compression 有权

    公开(公告)号：US11288016B2

    公开(公告)日：2022-03-29

    申请号：US17084289

    申请日：2020-10-29

    Applicant: Micron Technology, Inc.

    Inventor： Sebastien Andre Jean

    IPC: G06F12/00 ,  G06F3/06 ,  G11C16/04 ,  G11C16/10

    Abstract: Apparatus and methods are disclosed, including providing available data operations for the storage system processor to a host processor, identifying data operations to be performed by the storage system processor, and assigning identified data operations to the storage system processor to reduce bus traffic between the host processor and the storage system processor, to improve host processor performance, and to reduce energy use by the host processor.

    Reflow protection
    39.
    发明授权
    Reflow protection 有权

    公开(公告)号：US11222692B2

    公开(公告)日：2022-01-11

    申请号：US16915537

    申请日：2020-06-29

    Applicant: Micron Technology, Inc.

    Inventor： Sebastien Andre Jean ,  Ting Luo

    IPC: G11C11/56 ,  G11C16/34 ,  G11C16/10

    Abstract: Devices and techniques to reduce corruption of received data during assembly are disclosed herein. A memory device can perform operations to store received data, including preloaded data, in a first mode until the received data exceeds a threshold amount, and to transition from the first mode to a second mode after the received data exceeds the threshold amount.

    INTERNAL COMMUNICATION INTERFACE MANAGEMENT
    40.
    发明申请
    INTERNAL COMMUNICATION INTERFACE MANAGEMENT 有权

    公开(公告)号：US20210342099A1

    公开(公告)日：2021-11-04

    申请号：US17373239

    申请日：2021-07-12

    Applicant: Micron Technology, Inc.

    Inventor： Sebastien Andre Jean

    IPC: G06F3/06 ,  G06F13/16 ,  H03M7/30 ,  G11C16/04

    Abstract: Apparatus and methods are disclosed, including enabling communication between a memory controller and multiple memory devices of a storage system using a storage-system interface, the multiple memory devices each comprising a device controller and a group of non-volatile memory cells, and compressing data using at least one of the device controllers prior to transfer over the storage-system interface to improve an effective internal data transmission speed of the storage system.

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