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31.发明授权公开(公告)号：US11749359B2
公开(公告)日：2023-09-05
申请号：US17702525
申请日：2022-03-23
Applicant: Micron Technology, Inc.
Inventor： Hong-Yan Chen , Yingda Dong
CPC classification number: G11C16/3436 , G11C16/08 , G11C16/10 , G11C16/26 , G11C16/3413
Abstract: Control logic in a memory device initiates a program operation on the memory device, and causes a program voltage to be applied to a selected wordline of the memory array during a program phase of the program operation. The control logic further causes a select gate drain coupled with a string of memory cells in the memory array to deactivate during a recovery phase after applying the program voltage, wherein the string of memory cells comprises a plurality of memory cells, and wherein each memory cell of the plurality of memory cells is coupled to a corresponding wordline of a plurality of wordlines in the memory array.
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公开(公告)号：US20230195328A1
公开(公告)日：2023-06-22
申请号：US18082803
申请日：2022-12-16
Applicant: Micron Technology, Inc.
Inventor： Ching-Huang Lu , Yingda Dong , Sampath K. Ratnam
IPC: G06F3/06
CPC classification number: G06F3/0619 , G06F3/0679 , G06F3/0652
Abstract: Control logic in a memory device executes a programming operation to program a memory cell of a set of memory cells to a programming level. A first erase sub-operation is executed to erase the memory cell to a first threshold voltage level, the first erase sub-operation including applying, to the memory cell, a first erase pulse having a first erase voltage level. A second erase sub-operation is executed to erase the memory cell to a second threshold voltage level, the second erase sub-operation including applying, to the memory cell, a second erase pulse having a second erase voltage level, where the first erase voltage level of the first erase pulse is lower than the second erase voltage level of the second erase pulse.
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33.发明申请公开(公告)号：US20230044240A1
公开(公告)日：2023-02-09
申请号：US17970459
申请日：2022-10-20
Applicant: Micron Technology, Inc.
Inventor： Ching-Huang Lu , Vinh Q. Diep , Zhengyi Zhang , Yingda Dong
Abstract: Processing logic in a memory device initiates a program operation on a memory array, the program operation comprising a program phase and a program verify phase. The processing logic further causes a negative voltage signal to be applied to a first selected word line of a block of the memory array during the program verify phase of the program operation, wherein the first selected word line is coupled to a corresponding first memory cell of a first plurality of memory cells in a string of memory cells in the block, wherein the first selected word line is associated with the program operation.
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公开(公告)号：US11488677B2
公开(公告)日：2022-11-01
申请号：US17247435
申请日：2020-12-10
Applicant: Micron Technology, Inc.
Inventor： Kalyan Chakravarthy Kavalipurapu , George Matamis , Yingda Dong , Chang H. Siau
Abstract: A memory device includes a memory array of memory cells and control logic, operatively coupled with the memory array. The control logic is to perform operations, which include causing the memory cells to be programmed with an initial voltage distribution representing multiple logical states; causing the memory cells to be programmed with a subsequent voltage distribution representing a subset of the multiple logical states at a higher voltage than that of the initial voltage distribution, wherein the subset of the multiple logical states is compacted above a program verify voltage level for the subsequent voltage distribution; and causing a first program verify operation of the subsequent voltage distribution to be performed on the memory cells to verify one or more voltage levels of the subsequent voltage distribution.
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35.发明申请公开(公告)号：US20220215890A1
公开(公告)日：2022-07-07
申请号：US17702525
申请日：2022-03-23
Applicant: Micron Technology, Inc.
Inventor： Hong-Yan Chen , Yingda Dong
Abstract: Control logic in a memory device initiates a program operation on the memory device, and causes a program voltage to be applied to a selected wordline of the memory array during a program phase of the program operation. The control logic further causes a select gate drain coupled with a string of memory cells in the memory array to deactivate during a recovery phase after applying the program voltage, wherein the string of memory cells comprises a plurality of memory cells, and wherein each memory cell of the plurality of memory cells is coupled to a corresponding wordline of a plurality of wordlines in the memory array.
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Patent Agency Ranking
36.发明授权公开(公告)号：US11282582B2
公开(公告)日：2022-03-22
申请号：US16946273
申请日：2020-06-12
Applicant: Micron Technology, Inc.
Inventor： Hong-Yan Chen , Yingda Dong
Abstract: Control logic in a memory device initiates a program operation on the memory device, the program operation comprising a program phase, a program recovery phase, a program verify phase, and a program verify recovery phase. The control logic further causes a negative voltage signal to be applied to a first plurality of word lines of a data block of the memory device during the program verify recovery phase of the program operation, wherein each of the first plurality of word lines is coupled to a corresponding memory cell of a first plurality of memory cells in a string of memory cells in the data block, the first plurality of word lines comprising a selected word line associated with the program operation and one or more data word lines adjacent to the selected word line.
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公开(公告)号：US20210166773A1
公开(公告)日：2021-06-03
申请号：US17078161
申请日：2020-10-23
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Jun Xu , Yingda Dong
Abstract: A memory might include a common source, a first data line and a second data line, an array of memory cells, a plurality of access lines, and a controller. The array of memory cells might include a first string of memory cells selectively connected between the first data line and the common source and a second string of memory cells selectively connected between the second data line and the common source. Each access line of the plurality of access lines might be connected to a control gate of a respective memory cell of the first string of memory cells and a control gate of a respective memory cell of the second string of memory cells. The controller may access the array of memory cells. The controller might be configured to implement a source-side seeding operation concurrently with a data line set operation.
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公开(公告)号：US20250151275A1
公开(公告)日：2025-05-08
申请号：US19018707
申请日：2025-01-13
Applicant: Micron Technology, Inc.
Inventor： Haitao Liu , Kamal M. Karda , Albert Fayrushin , Yingda Dong
Abstract: Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a memory cell included in a memory cell string; the memory cell including charge storage structure and channel structure separated from the charge storage structure by a dielectric structure; a first control gate associated with the memory cell and located on a first side of the charge storage structure and a first side of the channel structure; and a second control gate associated with the memory cell and electrically separated from the first control gate, the second control gate located on a second side of the charge storage structure and a second side of the channel structure.
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39.发明申请公开(公告)号：US20250140322A1
公开(公告)日：2025-05-01
申请号：US18768974
申请日：2024-07-10
Applicant: Micron Technology, Inc.
Inventor： Shyam Sunder Raghunathan , Yingda Dong , Akira Goda , Leo Raimondo
Abstract: Erase operations can be performed selectively on one of erase blocks or a memory array coupled to the same string by creating a pseudo PN junction that is located adjacent to the selected erase block. The pseudo PN junction is created by including channel inversion at least on those portions of the string coupled to unselected erase blocks, which further creates a flow of electrons. As a result of the channel inversion (along with channel accumulation created adjacent to the channel inversion), the flow of gate induced drain leakage (GIDL) holes are further generated from the pseudo PN junction and GIDL holes are induced to tunnel into memory cells of the selected erase block.
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40.发明公开公开(公告)号：US20240244845A1
公开(公告)日：2024-07-18
申请号：US18622671
申请日：2024-03-29
Applicant: Micron Technology, Inc.
Inventor： Yifen Liu , Yan Song , Albert Fayrushin , Naiming Liu , Yingda Dong , George Matamis
IPC: H10B43/27 , H01L23/522 , H10B43/10 , H10B43/35 , H10B43/40
CPC classification number: H10B43/27 , H01L23/5226 , H10B43/10 , H10B43/35 , H10B43/40
Abstract: An electronic device comprises a stack of alternating dielectric materials and conductive materials, a pillar region extending vertically through the stack, an oxide material within the pillar region and laterally adjacent to the dielectric materials and the conductive materials of the stack, and a storage node laterally adjacent to the oxide material and within the pillar region. A charge confinement region of the storage node is in horizontal alignment with the conductive materials of the stack. A height of the charge confinement region in a vertical direction is less than a height of a respective, laterally adjacent conductive material of the stack in the vertical direction. Related methods and systems are also disclosed.
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