公开(公告)号：US20240071816A1

公开(公告)日：2024-02-29

申请号：US17896919

申请日：2022-08-26

Applicant: Micron Technology, Inc.

Inventor： Alyssa N. Scarbrough ,  Lifang Xu ,  Jordan D. Greenlee

IPC: H01L21/768 ,  H01L23/535 ,  H01L27/11526 ,  H01L27/11573

CPC classification number: H01L21/76816 ,  H01L21/76805 ,  H01L21/76846 ,  H01L21/76865 ,  H01L21/76895 ,  H01L23/535 ,  H01L27/11526 ,  H01L27/11573

Abstract: Methods, systems, and devices for staircase formation in a memory array are described. A liner composed of a first liner material may be deposited on a tread and a first portion of the liner may be doped. After doping the first portion of the liner, a second portion of the liner may be converted into a second liner material using a chemical process. After converting the second portion of the liner into the second liner material, the first portion of the liner material may be removed so that a subsequent removal process can expose a first sub-tread. After exposing the first sub-tread, the second portion of the liner may be removed so that a second sub-tread is exposed.

公开(公告)号：US11903211B2

公开(公告)日：2024-02-13

申请号：US17647238

申请日：2022-01-06

Applicant: Micron Technology, Inc.

Inventor： Lifang Xu ,  John D. Hopkins ,  Roger W. Lindsay ,  Shuangqiang Luo

IPC: H10B43/40 ,  H01L23/522 ,  H01L23/528 ,  H01L23/535 ,  H01L21/768 ,  H10B41/41

CPC classification number: H10B43/40 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76826 ,  H01L21/76877 ,  H01L21/76895 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/535 ,  H10B41/41

Abstract: A method of forming a microelectronic device comprises forming isolated nitride structures on steps of stair step structures comprising stacked tiers comprising alternating levels of a first insulative material and a second insulative material, forming a photoresist material over some of the stair step structures, and replacing the isolated nitride structures and the second insulative material with an electrically conductive material to respectively form conductive pad structures and electrically conductive lines. Related microelectronic devices and electronic devices are also disclosed.

公开(公告)号：US20230397421A1

公开(公告)日：2023-12-07

申请号：US17876271

申请日：2022-07-28

Applicant: Micron Technology, Inc.

Inventor： Mallesh Rajashekharaiah ,  Lifang Xu ,  Nancy M. Lomeli

IPC: H01L27/11582 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157

CPC classification number: H01L27/11582 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157

Abstract: Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes tiers located one over another, the tiers including conductive materials that form part of respective control gates for memory cells of the apparatus; a staircase structure formed in the tiers, the conductive materials including respective portions that collectively form a part of the staircase structure, the staircase structure including a sidewall on a side of the staircase structure; a dielectric liner formed on the sidewall; recesses formed in respective tiers and adjacent the sidewall such that respective portions of the dielectric liner are located in the recesses; and a contact structure extending through a portion of the dielectric liner, wherein the portions of the dielectric liner are between the contract structure and the conductive materials.

公开(公告)号：US20230328975A1

公开(公告)日：2023-10-12

申请号：US18207499

申请日：2023-06-08

Applicant: Micron Technology, Inc.

Inventor： Shuangqiang Luo ,  Lifang Xu ,  Indra V. Chary

IPC: H10B41/40 ,  H10B43/27 ,  H10B41/27 ,  H10B41/10 ,  H10B43/10 ,  H10B43/40

CPC classification number: H10B41/27 ,  H10B41/10 ,  H10B41/40 ,  H10B43/10 ,  H10B43/27 ,  H10B43/40

Abstract: Some embodiments include an integrated assembly having a first memory region, a second memory region, and an intermediate region between the memory regions. A stack extends across the memory regions and the intermediate region. The stack includes alternating conductive levels and insulative levels. Channel-material-pillars are arranged within the memory regions. Memory-block-regions extend longitudinally across the memory regions and the intermediate region. Staircase regions are within the intermediate region. Each of the staircase regions laterally overlaps two of the memory-block-regions. First panel regions extend longitudinally across at least portions of the staircase regions. Second panel regions extend longitudinally and provide lateral separation between adjacent memory-block-regions. The second panel regions are of laterally different dimensions than the first panel regions and/or are compositionally different than the first panel regions. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US11785775B2

公开(公告)日：2023-10-10

申请号：US17153740

申请日：2021-01-20

Applicant: Micron Technology, Inc.

Inventor： Lifang Xu ,  Shuangqiang Luo ,  Harsh Narendrakumar Jain ,  Nancy M. Lomeli ,  Christopher J. Larsen

IPC: H10B43/35 ,  H01L23/522 ,  H01L23/00 ,  H01L23/528 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B43/27 ,  H10B43/40

CPC classification number: H10B43/35 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/562 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B43/27 ,  H10B43/40

Abstract: A method of forming a microelectronic device includes forming a microelectronic device structure. The microelectronic device structure includes a stack structure having an alternating sequence of conductive structures and insulative structures, an upper stadium structure, a lower stadium structure, and a crest region defined between a first stair step structure of the upper stadium structure and a second stair step structure of the lower stadium structure. The stack structure further includes pillar structures extending through the stack structure and dielectric structures interposed between neighboring pillar structures within the upper stadium structure. The method further includes forming a trench in the crest region of the stack structure between two dielectric structures of the dielectric structures on opposing sides of another dielectric structure and filling the trench with a dielectric material. The trench partially overlaps with the dielectric structures.

公开(公告)号：US20230307350A1

公开(公告)日：2023-09-28

申请号：US17701509

申请日：2022-03-22

Applicant: Micron Technology, Inc.

Inventor： Lifang Xu ,  Indra V. Chary ,  Richard J. Hill

IPC: H01L23/522 ,  H01L23/528 ,  H01L23/535 ,  H01L21/768

CPC classification number: H01L23/5221 ,  H01L23/5283 ,  H01L23/535 ,  H01L21/76816 ,  H01L21/76895

Abstract: A microelectronic device includes a stack structure having blocks separated by dielectric slot structures and each including a vertically alternating sequence of conductive structures and insulative structures arranged in tiers. At least one of the blocks includes an upper stadium structure, two crest regions, a lower stadium structure, and two bridge regions. The upper stadium structure extends from and between two of the dielectric slot structures, and includes staircase structures having steps including edges of some of the tiers. The two crest regions are horizontally offset from the upper stadium structure. The lower stadium structure is below the upper stadium structure, is interposed between the two crest regions, and includes additional staircase structures. The two bridge regions are interposed between the lower stadium structure and the two of the dielectric slot structures, and extend between the two crest regions. Related memory devices, electronic systems, and methods are also described.

公开(公告)号：US11765902B2

公开(公告)日：2023-09-19

申请号：US17491752

申请日：2021-10-01

Applicant: Micron Technology, Inc.

Inventor： John D. Hopkins ,  Lifang Xu

IPC: H10B43/27 ,  H10B41/27 ,  H10B41/35 ,  H10B43/35 ,  H10B41/10 ,  H10B43/10

CPC classification number: H10B43/27 ,  H10B41/27 ,  H10B41/35 ,  H10B43/35 ,  H10B41/10 ,  H10B43/10

Abstract: A memory array comprising strings of memory cells comprises a vertical stack comprising alternating insulative tiers and conductive tiers. Channel-material strings of memory cells are in the stack. The channel-material strings project upwardly from material of an uppermost of the tiers. A first insulator material is above the material of the uppermost tier directly against sides of channel material of the upwardly-projecting channel-material strings. The first insulator material comprises at least one of (a) and (b), where (a): silicon, nitrogen, and one or more of carbon, oxygen, boron, and phosphorus, and (b): silicon carbide. Second insulator material is above the first insulator material. The first and second insulator materials comprise different compositions relative one another. Conductive vias in the second insulator material are individually directly electrically coupled to individual of the channel-material strings. Other embodiments, including methods, are disclosed.

公开(公告)号：US11665894B2

公开(公告)日：2023-05-30

申请号：US17249552

申请日：2021-03-04

Applicant: Micron Technology, Inc.

Inventor： Christopher J. Larsen ,  Lifang Xu

IPC: H10B41/27 ,  H10B43/27 ,  H01L27/11556 ,  H01L21/768 ,  H01L27/11582 ,  H01L23/538 ,  G11C5/06

CPC classification number: H01L27/11556 ,  G11C5/06 ,  H01L21/76877 ,  H01L23/5381 ,  H01L23/5384 ,  H01L23/5386 ,  H01L27/11582

Abstract: A microelectronic device comprises a stack structure comprising blocks separated from one another by dielectric slot structures. At least one of the blocks comprises two crest regions, a stadium structure interposed between the two crest regions in a first horizontal direction, and two bridge regions neighboring opposing sides of the stadium structure in a second horizontal direction. A filled trench vertically overlies and is within horizontal boundaries of the stadium structure of the at least one of the blocks. The filled trench comprises a dielectric liner material on the opposing staircase structures of the stadium structure and on inner sidewalls of the two bridge regions, and dielectric structures on and having a different material composition than the dielectric liner material. The dielectric structures are substantially confined within horizontal areas of the steps of the stadium structure. Memory devices, electronic systems, and methods of forming microelectronic devices are also described.

公开(公告)号：US11658132B2

公开(公告)日：2023-05-23

申请号：US17559321

申请日：2021-12-22

Applicant: Micron Technology, Inc.

Inventor： Rohit Kothari ,  Lifang Xu ,  Jian Li

IPC: H01L23/522 ,  H01L23/528 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11582 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11529 ,  H01L23/00

CPC classification number: H01L23/562 ,  H01L23/5226 ,  H01L23/5283 ,  H01L27/1157 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11573 ,  H01L27/11582

Abstract: Some embodiments include an integrated assembly having a semiconductor die with memory array regions and one or more regions peripheral to the memory array regions. A stack of alternating insulative and conductive levels extends across the memory array regions and passes into at least one of the peripheral regions. The stack generates bending stresses on the die. At least one stress-moderating region extends through the stack and is configured to alleviate the bending stresses.

公开(公告)号：US11563022B2

公开(公告)日：2023-01-24

申请号：US16550252

申请日：2019-08-25

Applicant: Micron Technology, Inc.

Inventor： Lifang Xu ,  Indra V. Chary ,  Justin B. Dorhout ,  Jian Li ,  Haitao Liu ,  Paolo Tessariol

IPC: H01L29/76 ,  H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L27/1157

Abstract: A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Operative channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. The operative channel-material strings in the laterally-spaced memory blocks comprise part of a memory plane. An elevationally-extending wall is in the memory plane laterally-between immediately-laterally-adjacent of the memory blocks and that completely encircles an island that is laterally-between immediately-laterally-adjacent of the memory blocks in the memory plane. Other embodiments, including method are disclosed.