公开(公告)号：US06555461B1

公开(公告)日：2003-04-29

申请号：US09884059

申请日：2001-06-20

申请人： Christy Mei-Chu Woo ,  Suzette K. Pangrle ,  Minh Van Ngo

发明人： Christy Mei-Chu Woo ,  Suzette K. Pangrle ,  Minh Van Ngo

IPC分类号： H01L214763

CPC分类号： H01L21/76831 ,  H01L21/76802 ,  H01L21/76807 ,  H01L21/76832 ,  H01L21/76844 ,  H01L21/76846 ,  H01L21/76873 ,  H01L23/5226 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for forming a metal interconnect structure provides a conformal layer of barrier material, such as a nitride, within a patterned opening in a dielectric layer. The barrier material is deposited after the opening is etched to the dielectric layer, stopping on a diffusion barrier. A first layer of a metal barrier material, such as tantalum, is conformally deposited on the barrier material. A directional etch is performed that removes horizontal nitride and tantalum, leaving the nitride and tantalum on the sidewalls of the patterned opening. The barrier material prevents contamination of the dielectric layer from conductive material, such as copper, during the etching of the diffusion barrier overlying the conductive material, and during subsequent sputter etch cleaning. A thin, second metal layer is conformally deposited and forms a suitable barrier on the sidewalls of the opening, while providing low contact resistance between the second metal layer and the underlying substrate.

摘要翻译： 用于形成金属互连结构的方法在电介质层的图案化开口内提供诸如氮化物之类的阻挡材料的共形层。 在将开口蚀刻到电介质层上之后，阻挡材料沉积，停止在扩散阻挡层上。 诸如钽的金属阻挡材料的第一层被共形沉积在阻挡材料上。 执行定向蚀刻，其去除水平氮化物和钽，留下图案化开口的侧壁上的氮化物和钽。 阻挡材料在覆盖导电材料的扩散阻挡层的蚀刻期间以及在随后的溅射蚀刻清洁期间防止介电层从导电材料（例如铜）中的污染。 薄的第二金属层被共形沉积，并且在开口的侧壁上形成合适的阻挡层，同时在第二金属层和下面的基底之间提供低的接触电阻。

公开(公告)号：US06455422B1

公开(公告)日：2002-09-24

申请号：US09705444

申请日：2000-11-02

申请人： Minh Van Ngo ,  Christy Mei-Chu Woo

发明人： Minh Van Ngo ,  Christy Mei-Chu Woo

IPC分类号： H01L2144

CPC分类号： H01L21/76834 ,  H01L21/76801 ,  H01L21/76828 ,  H01L21/76883

摘要： An integrated circuit and manufacturing method therefor is provided having a semiconductor substrate with a semiconductor device. A device dielectric layer is formed on the semiconductor substrate, and a channel dielectric layer formed on the device dielectric layer has an opening formed therein. A barrier layer of titanium, tantalum, tungsten, or a nitride of the aforegoing is deposited to line the opening, and a copper or copper alloy conductor core is deposited to fill the channel opening over the barrier layer. After planarization of the conductor core and the barrier layer, an ammonia, nitrogen hydride, or hydrogen plasma treatment is performed below 300° C. to reduce the residual oxide on the conductor core material. The plasma treatment is followed by the deposition of a silicon nitride capping layer performed below 300° C. After the reducing and deposition process, a densification process is performed between 380° C. and 420° C. to density the capping layer to enhance the quality of the silicon nitride layer.

摘要翻译： 提供了具有半导体器件的半导体衬底的集成电路及其制造方法。 在半导体基板上形成器件电介质层，在器件电介质层上形成的沟道电介质层形成有开口部。 沉积钛，钽，钨或前述氮化物的阻挡层以对开口进行排列，并且沉积铜或铜合金导体芯以填充阻挡层上的通道开口。 在导体芯和阻挡层平坦化之后，在300℃以下进行氨，氮化氢或氢等离子体处理以减少导体芯材上的残余氧化物。 等离子体处理之后，在300℃以下进行氮化硅覆盖层的沉积。在还原和沉积工艺之后，在380℃和420℃之间进行致密化过程以密封覆盖层以增强 氮化硅层的质量。

公开(公告)号：US06617176B1

公开(公告)日：2003-09-09

申请号：US10152861

申请日：2002-05-21

申请人： John E. Sanchez, Jr. ,  Pin-Chin Connie Wang ,  Christy Mei-Chu Woo ,  Paul R. Besser

发明人： John E. Sanchez, Jr. ,  Pin-Chin Connie Wang ,  Christy Mei-Chu Woo ,  Paul R. Besser

IPC分类号： H01L2166

CPC分类号： H01L22/24 ,  G01N1/32 ,  H01L22/34

摘要： A method (M) of determining the effectiveness of a deposited thin conformal barrier layer (30) by forming a test specimen and measuring the copper (Cu) penetration from a metallization layer (40) through the barrier layer (30) (e.g., refractory metals, their nitrides, their carbides, or their other compounds), through a thin insulating dielectric layer (20) (e.g., SiO2), and into a semiconductor (10) substrate (e.g., Si), wherein the interaction between the migrating metal ions and the semiconductor ions are detected/monitored, and wherein the detection/monitoring comprises (1) stripping at least a portion of the insulating dielectric layer (20) and the barrier layer (30) and (2) examining the semiconductor substrate (10) surface of the test specimen, thereby improving interconnect reliability, enhancing electromigration resistance, improving corrosion resistance, reducing copper diffusion, and a test specimen device thereby formed.

摘要翻译： 通过形成测试样品并测量从金属化层（40）穿过阻挡层（30）（例如耐火材料）的铜（Cu）渗透性来确定沉积的薄共形阻挡层（30）的有效性的方法（M） 金属，其氮化物，它们的碳化物或其它化合物）通过薄的绝缘介电层（20）（例如SiO 2）和半导体（10）衬底（例如Si）中，其中迁移金属 离子和半导体离子被检测/监测，并且其中检测/监测包括（1）剥离绝缘介电层（20）和阻挡层（30）的至少一部分和（2）检查半导体衬底（10） ）表面，从而提高互连可靠性，提高耐迁移性，提高耐腐蚀性，减少铜扩散，从而形成试样装置。

公开(公告)号：US06562718B1

公开(公告)日：2003-05-13

申请号：US09729700

申请日：2000-12-06

申请人： Qi Xiang ,  Ercan Adem ,  Jacques J. Bertrand ,  Paul R. Besser ,  Matthew S. Buynoski ,  John C. Foster ,  Paul L. King ,  George J. Kluth ,  Minh V. Ngo ,  Eric N. Paton ,  Christy Mei-Chu Woo

发明人： Qi Xiang ,  Ercan Adem ,  Jacques J. Bertrand ,  Paul R. Besser ,  Matthew S. Buynoski ,  John C. Foster ,  Paul L. King ,  George J. Kluth ,  Minh V. Ngo ,  Eric N. Paton ,  Christy Mei-Chu Woo

IPC分类号： H01L2144

CPC分类号： H01L29/66507 ,  H01L21/28097

摘要： A method of forming a fully silicidized gate of a semiconductor device includes forming silicide in active regions and a portion of a gate. A shield layer is blanket deposited over the device. The top surface of the gate electrode is then exposed. A refractory metal layer is deposited and annealing is performed to cause the metal to react with the gate and fully silicidize the gate, with the shield layer protecting the active regions of the device from further silicidization to thereby prevent spiking and current leakage in the active regions.

摘要翻译： 形成半导体器件的完全硅化栅极的方法包括在有源区和门的一部分中形成硅化物。 屏蔽层被覆盖在该器件上。 然后露出栅电极的顶表面。 沉积难熔金属层并进行退火以使金属与栅极反应并使栅极完全硅化，屏蔽层保护器件的有源区不受另外的硅化，从而防止有源区中的峰值和电流泄漏 。

公开(公告)号：US06806172B1

公开(公告)日：2004-10-19

申请号：US09826078

申请日：2001-04-05

申请人： Christy Mei-Chu Woo ,  Eric N. Paton ,  Susan Tover

发明人： Christy Mei-Chu Woo ,  Eric N. Paton ,  Susan Tover

IPC分类号： H01L21425

CPC分类号： H01L29/665 ,  H01L21/324 ,  H01L29/7833

摘要： Nickel film formation is implemented by heating a deposition chamber during deposition of nickel on a substrate or between processing of two or more substrates or both. Embodiments include forming a nickel silicide on a composite having an exposed silicon surface by introducing the substrate to a PVD chamber having at least one heating element for heating the chamber and depositing a layer of nickel directly on the exposed silicon surface of the composite while concurrently heating the chamber with the heating element.

摘要翻译： 通过在将镍沉积在基底上或在两个或更多个基底或两者的处理之间加热沉积室来实现镍膜形成。 实施例包括在具有暴露的硅表面的复合材料上形成硅化镍，通过将衬底引入具有至少一个用于加热室的加热元件的PVD室，并将镍层直接沉积在复合材料的暴露的硅表面上，同时加热 具有加热元件的室。

公开(公告)号：US06472757B2

公开(公告)日：2002-10-29

申请号：US09758994

申请日：2001-01-11

申请人： Amit P. Marathe ,  Pin-Chin Connie Wang ,  Christy Mei-Chu Woo

发明人： Amit P. Marathe ,  Pin-Chin Connie Wang ,  Christy Mei-Chu Woo

IPC分类号： H01L23528

CPC分类号： H01L21/76844 ,  H01L21/76838 ,  H01L21/76873 ,  H01L21/76874 ,  H01L23/5226 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53252 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit and manufacturing method therefor is provided having a semiconductor substrate with a semiconductor device. A device dielectric layer is formed on the semiconductor substrate. A first dielectric layer on the device dielectric layer has an opening formed therein including a conductor reservoir volume. A barrier layer lines the channel opening. A conductor core fills the opening over the barrier layer. A second dielectric layer is formed on the first dielectric layer and has a second channel and via opening provided therein. A barrier layer lines the second channel and via opening except over the first channel opening. A conductor core fills the second channel and via opening over the barrier layer and the first conductor core to form the second channel and via. The conductor reservoir volume provides a supply of conductor material to prevent the formation of voids in the first channel and in the via.

公开(公告)号：US06455938B1

公开(公告)日：2002-09-24

申请号：US09905479

申请日：2001-07-13

申请人： Pin-Chin Connie Wang ,  Amit P. Marathe ,  Christy Mei-Chu Woo

发明人： Pin-Chin Connie Wang ,  Amit P. Marathe ,  Christy Mei-Chu Woo

IPC分类号： H01L2945

CPC分类号： H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit and manufacturing method therefor is provided for an integrated circuit on a semiconductor substrate grated circuit having a semiconductor device. A dielectric layer is on the semiconductor substrate and has an opening provided therein. A barrier layer lines the opening, and a first conductor core fills the opening over the barrier layer. A second dielectric layer is formed on the first dielectric layer and has a second channel and via opening provided therein. A shunt layer is in the via opening above the conductor core. A barrier layer lines the second channel and via opening over the shunt layer and the second dielectric layer. A conductor core fills the second channel and via opening over the barrier layer and the first conductor core to form the second channel and via.

摘要翻译： 提供了一种用于具有半导体器件的半导体衬底格栅电路上的集成电路的集成电路及其制造方法。 电介质层位于半导体衬底上，其中设有开口。 阻挡层对开口进行排列，并且第一导体芯填充阻挡层上的开口。 第二电介质层形成在第一电介质层上并具有设置在其中的第二通道和通孔。 并联层位于导体芯上方的通孔中。 阻挡层将第二通道和通过开口穿过并联层和第二介电层。 导体芯填充第二通道并通过阻挡层和第一导体芯上的开口形成第二通道和通孔。

公开(公告)号：US06270635B1

公开(公告)日：2001-08-07

申请号：US09299871

申请日：1999-04-27

申请人： Christy Mei-Chu Woo

发明人： Christy Mei-Chu Woo

IPC分类号： C25B1500

CPC分类号： C25D21/12 ,  C25D7/12 ,  C25D17/001

摘要： A small plating solution reservoir of about 250-cc or less volume is used to provide plating of one wafer at a time with a precisely controlled, repeatable, plating solution. The reservoir is connected to basic plating solution and additives which are provided in desired concentrations by a valving and control system for single wafers and drained after the single wafer is plated.

摘要翻译： 使用约250cc或更小体积的小电镀溶液储存器，以一次精确控制，可重复的电镀溶液提供一个晶片的电镀。 储存器通过用于单个晶片的阀门和控制系统连接到基本电镀溶液和以所需浓度提供的添加剂，并在单个晶片被镀覆之后排出。

公开(公告)号：US6143656A

公开(公告)日：2000-11-07

申请号：US176891

申请日：1998-10-22

申请人： Kai Yang ,  Steven Avanzino ,  Christy Mei-Chu Woo

发明人： Kai Yang ,  Steven Avanzino ,  Christy Mei-Chu Woo

IPC分类号： H01L21/321 ,  H01L21/768 ,  H01L21/44

CPC分类号： H01L21/3212 ,  H01L21/76802

摘要： Copper metalization is planarized by CMP employing a slurry which avoids scratching the copper surface and is highly selective to the underlying barrier layer. Embodiments include CMP a copper filled damascene opening using a slurry comprising about 0.2 to about 0.7 wt. % Al.sub.2 O.sub.3 and about 0.2 to about 2 wt. % oxalic acid to achieve a RMS no greater than about 10 .ANG..

摘要翻译： 铜的金属化通过CMP平坦化，其使用避免划伤铜表面并且对下面的阻挡层具有高度选择性的浆料。 实施方案包括使用包含约0.2至约0.7重量％的浆料的CMP铜填充镶嵌开口。 ％Al 2 O 3和约0.2至约2重量％ ％草酸达到RMS不大于约10 ANGSTROM。

公开(公告)号：US6103085A

公开(公告)日：2000-08-15

申请号：US205584

申请日：1998-12-04

申请人： Christy Mei-Chu Woo ,  John A. Iacoponi ,  Kai Yang

发明人： Christy Mei-Chu Woo ,  John A. Iacoponi ,  Kai Yang

IPC分类号： C25D5/08 ,  C25D7/12 ,  C25D17/00 ,  H01L21/288 ,  C25D5/04

CPC分类号： H01L21/2885 ,  C25D17/001 ,  C25D17/008 ,  C25D5/08

摘要： Workpieces, such as semiconductor wafers, are electroplated with improved thickness uniformity by providing a diffuser member intermediate the cathode and anode of a fountain-type electroplating apparatus. The diffuser or member has a pattern of openings specifically designed to prevent channeling and/or selective directing of electrolyte towards the workpiece. In one embodiment, the diffuser member comprises a spiral-shaped pattern of openings originating at the center of the diffuser member and extending to the periphery thereof.

摘要翻译： 通过在喷泉型电镀设备的阴极和阳极之间设置扩散件，电工工件（例如半导体晶片）电镀具有改进的厚度均匀性。 扩散器或构件具有专门设计成防止电解液向工件的引导和/或选择性引导的开口图案。 在一个实施例中，扩散器构件包括源自扩散器构件的中心并延伸到其周边的开口的螺旋形图案。