公开(公告)号：US07713834B2

公开(公告)日：2010-05-11

申请号：US12205361

申请日：2008-09-05

申请人： Haihong Wang ,  Minh-Van Ngo ,  Qi Xiang ,  Paul R. Besser ,  Eric N. Paton ,  Ming-Ren Lin

发明人： Haihong Wang ,  Minh-Van Ngo ,  Qi Xiang ,  Paul R. Besser ,  Eric N. Paton ,  Ming-Ren Lin

IPC分类号： H01L21/76

CPC分类号： H01L21/76224 ,  H01L21/823481 ,  H01L29/1054

摘要： A method of manufacturing an integrated circuit (IC) utilizes a shallow trench isolation (STI) technique. The shallow trench isolation technique is used in strained silicon (SMOS) process. The liner for the trench is formed from a semiconductor or metal layer which is deposited in a low temperature process which reduces germanium outgassing. The low temperature process can be a ALD process.

摘要翻译： 集成电路（IC）的制造方法利用浅沟槽隔离（STI）技术。 浅沟槽隔离技术用于应变硅（SMOS）工艺。 用于沟槽的衬垫由半导体或金属层形成，该半导体或金属层在低温过程中沉积，这降低了锗除气。 低温过程可以是ALD过程。

公开(公告)号：US07670915B1

公开(公告)日：2010-03-02

申请号：US10791096

申请日：2004-03-01

申请人： Errol Todd Ryan ,  Paul R. Besser ,  Simon Siu-Sing Chan ,  Robert J. Chiu ,  Mehrdad Mahanpour ,  Minh Van Ngo

发明人： Errol Todd Ryan ,  Paul R. Besser ,  Simon Siu-Sing Chan ,  Robert J. Chiu ,  Mehrdad Mahanpour ,  Minh Van Ngo

IPC分类号： H01L21/20

CPC分类号： H01L21/28518 ,  H01L29/665 ,  H01L29/7833

摘要： A method of forming an integrated circuit with a semiconductor substrate is provided. A gate dielectric is formed on the semiconductor substrate, and a gate is formed on the gate dielectric. Source/drain junctions are formed in the semiconductor substrate. A silicide is formed on the source/drain junctions and on the gate. An interlayer dielectric having contact holes therein is formed above the semiconductor substrate. Contact liners are formed in the contact holes, and contacts are then formed over the contact liners. The contact liners are nitrides of the contact material, and formed at a temperature below the thermal budget for the silicide.

摘要翻译： 提供一种形成具有半导体衬底的集成电路的方法。 在半导体衬底上形成栅极电介质，在栅极电介质上形成栅极。 在半导体衬底中形成源极/漏极结。 在源极/漏极结和栅极上形成硅化物。 在半导体衬底的上方形成有具有接触孔的层间电介质。 接触衬垫形成在接触孔中，然后在接触衬垫上形成接触。 接触衬垫是接触材料的氮化物，并且在低于硅化物的热预算的温度下形成。

公开(公告)号：US07648886B2

公开(公告)日：2010-01-19

申请号：US10341863

申请日：2003-01-14

申请人： Minh-Van Ngo ,  Qi Xiang ,  Paul R. Besser ,  Eric N. Paton ,  Ming-Ren Lin

发明人： Minh-Van Ngo ,  Qi Xiang ,  Paul R. Besser ,  Eric N. Paton ,  Ming-Ren Lin

IPC分类号： H01L21/762

CPC分类号： H01L21/76224

摘要： A method of manufacturing an integrated circuit (IC) utilizes a shallow trench isolation (STI) technique. The shallow trench isolation technique is used in strained silicon (SMOS) process. The liner for the trench is formed to in a low temperature process which reduces germanium outgassing. The low temperature process can be a UVO, ALD, CVD, PECVD, or HDP process.

摘要翻译： 集成电路（IC）的制造方法利用浅沟槽隔离（STI）技术。 浅沟槽隔离技术用于应变硅（SMOS）工艺。 用于沟槽的衬垫形成为能够减少锗除气的低温过程。 低温过程可以是UVO，ALD，CVD，PECVD或HDP工艺。

公开(公告)号：US07060571B1

公开(公告)日：2006-06-13

申请号：US10777138

申请日：2004-02-13

申请人： Minh Van Ngo ,  Christy Woo ,  James Pan ,  Paul R. Besser ,  Jinsong Yin

发明人： Minh Van Ngo ,  Christy Woo ,  James Pan ,  Paul R. Besser ,  Jinsong Yin

IPC分类号： H01L21/336

CPC分类号： H01L21/28229 ,  H01L21/28079 ,  H01L21/28088 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545

摘要： Microminiaturized semiconductor devices are fabricated with a replacement metal gate and a high-k tantalum oxide or tantalum oxynitride gate dielectric with significantly reduced carbon. Embodiments include forming an opening in a dielectric layer by removing a removable gate, depositing a thin tantalum film, as by PVD at a thickness of 25 Å to 60 Å lining the opening, and then conducting thermal oxidation, as at a temperature of 100° C. to 500° C., in flowing oxygen or ozone to form a high-k tantalum oxide gate dielectric layer, or in oxygen and N2O or ozone and N2O ammonia to form a high-k tantalum oxynitride gate dielectric. Alternatively, oxidation can be conducted in an oxygen or ozone plasma to form the high-k tantalum oxide layer, or in a plasma containing N2O and oxygen or ozone to form the high-k tantalum oxynitride gate dielectric layer.

摘要翻译： 微型半导体器件由具有显着降低的碳的替代金属栅极和高k钽氧化物或氮氧化钽栅极电介质制成。 实施例包括通过去除可移除栅极来形成电介质层中的开口，沉积薄的钽膜，如通过PVD覆盖厚度为25埃至60埃的开口，然后在100℃的温度下进行热氧化 在500℃下，在流动的氧气或臭氧中形成高k氧化钽栅极电介质层，或在氧和N 2 O或臭氧和N 2 O 3 > O氨形成高k钽氮氧化物栅极电介质。 或者，可以在氧气或臭氧等离子体中进行氧化以形成高k钽氧化物层，或者在含有N 2 O的氧化物或臭氧的等离子体中进行氧化以形成高k氮氧化钽栅极 电介质层。

公开(公告)号：US06893910B1

公开(公告)日：2005-05-17

申请号：US10462670

申请日：2003-06-17

申请人： Christy Mei-Chu Woo ,  Paul R. Besser ,  Minh Van Ngo ,  James N. Pan ,  Jinsong Yin

发明人： Christy Mei-Chu Woo ,  Paul R. Besser ,  Minh Van Ngo ,  James N. Pan ,  Jinsong Yin

IPC分类号： H01L21/28 ,  H01L21/316 ,  H01L21/336 ,  H01L29/49 ,  H01L29/51 ,  H01L29/78 ,  H01L21/338 ,  H01L21/31 ,  H01L21/3205

CPC分类号： H01L21/28185 ,  H01L21/28079 ,  H01L21/28194 ,  H01L21/31683 ,  H01L29/4958 ,  H01L29/511 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66583 ,  H01L29/7833

摘要： A method for forming a semiconductor structure removes the temporary gate formed on the dielectric layer to expose a recess in which oxygen-rich CVD oxide is deposited. A tantalum layer is then deposited by low-power physical vapor deposition on the CVD oxide. Annealing is then performed to create a Ta2O5 region and a Ta region from the deposited oxide and Ta. This creates a low carbon-content Ta2O5 and a metallic Ta gate in a single process step.

摘要翻译： 用于形成半导体结构的方法去除形成在电介质层上的临时栅极以暴露其中沉积有富氧CVD氧化物的凹槽。 然后通过低功率物理气相沉积在CVD氧化物上沉积钽层。 然后进行退火以从沉积的氧化物和Ta形成Ta 2 O 5区域和Ta区域。 这在单一工艺步骤中产生低碳含量的Ta 2 O 5 O 5和金属Ta浇口。

公开(公告)号：US06727560B1

公开(公告)日：2004-04-27

申请号：US10360719

申请日：2003-02-10

申请人： James N. Pan ,  Paul R. Besser ,  Christy Woo ,  Minh Van Ngo ,  Jinsong Yin

发明人： James N. Pan ,  Paul R. Besser ,  Christy Woo ,  Minh Van Ngo ,  Jinsong Yin

IPC分类号： H01L2976

CPC分类号： H01L29/66545 ,  H01L21/28088 ,  H01L29/4966

摘要： A metal gate electrode is formed with an intrinsic electric field to modify its work function and the threshold voltage of the transistor. Embodiments include forming an opening in a dielectric layer by removing a removable gate, depositing one or more layers of tantalum nitride such that the nitrogen content increases from the bottom of the layer adjacent the gate dielectric layer upwardly. Other embodiments include forming the intrinsic electric field to control the work function by doping one or more metal layers and forming metal alloys. Embodiments further include the use of barrier layers when forming metal gate electrodes.

公开(公告)号：US06387767B1

公开(公告)日：2002-05-14

申请号：US09781448

申请日：2001-02-13

申请人： Paul R. Besser ,  Minh Van Ngo ,  Christy Mei-Chu Woo ,  George Jonathan Kluth

发明人： Paul R. Besser ,  Minh Van Ngo ,  Christy Mei-Chu Woo ,  George Jonathan Kluth

IPC分类号： H01L21336

CPC分类号： H01L29/665

摘要： Salicide processing is implemented with nitrogen-rich silicon nitride sidewall spacers that allow a metal silicide layer e.g., NiSi, to be formed over the polysilicon gate electrode and source/drain regions using salicide technology without associated bridging between the metal silicide layer on the gate electrode and the metal silicide layers over the source/drain regions. Bridging between a metal silicide e.g., nickel silicide, layer on a gate electrode and metal silicide layers on associated source/drain regions is avoided by forming nitrogen-rich silicon nitride sidewall spacers with increased nitrogen, thereby eliminating free Si available to react with the metal subsequently deposited and thus avoiding the formation of metal silicide on the sidewall spacers.

摘要翻译： 使用富含氮的氮化硅侧壁间隔物实现自杀处理，其允许使用硅化物技术在多晶硅栅极电极和源极/漏极区域上形成金属硅化物层，例如NiSi，而不会在栅极上的金属硅化物层之间相互桥接 和源极/漏极区域之间的金属硅化物层。通过形成具有增加的富氮氮化硅侧壁间隔物，避免了金属硅化物（例如，硅化镍），栅极上的层和相关源极/漏极区域上的金属硅化物层之间的结合 氮，从而消除可用于随后沉积的金属的游离Si，从而避免在侧壁间隔物上形成金属硅化物。

公开(公告)号：US06228761B1

公开(公告)日：2001-05-08

申请号：US09417840

申请日：1999-10-14

申请人： Minh Van Ngo ,  Paul R. Besser

发明人： Minh Van Ngo ,  Paul R. Besser

IPC分类号： H01L214763

CPC分类号： H01L21/76897 ,  H01L21/3144 ,  H01L21/3145 ,  H01L21/3185 ,  H01L21/76895

摘要： A method and arrangement for forming a local interconnect without weakening the field edge or disconnecting the diffusion region at the field edge introduces additional nitrogen from a nitrogen plasma into a nitrogen-containing etch stop layer (e.g., SiON) that has already been deposited by plasma enhanced chemical vapor deposition (PECVD), for example. The enriched nitrogen etch stop layer is harder to etch than conventional PECVD SiON so that when etching the dielectric layer in which the local interconnect material is to be subsequently deposited, the etching stops at the etch stop layer in a controlled manner. This prevents the unintentional etching of the silicide region and diffusion region at the field edge.

摘要翻译： 用于形成局部互连而不削弱场边缘或在场边缘处断开扩散区的方法和装置将来自氮等离子体的附加氮引入已经通过等离子体沉积的含氮蚀刻停止层（例如，SiON） 增强化学气相沉积（PECVD）。 富集的氮蚀刻停止层比常规PECVD SiON难以蚀刻，使得当蚀刻其中将要沉积局部互连材料的电介质层时，蚀刻以受控的方式在蚀刻停止层处停止。 这防止了在场边缘处的硅化物区域和扩散区域的无意蚀刻。

公开(公告)号：US06204136B1

公开(公告)日：2001-03-20

申请号：US09386466

申请日：1999-08-31

申请人： Simon S. Chan ,  Minh Van Ngo ,  Paul R. Besser ,  Angela T. Hui

发明人： Simon S. Chan ,  Minh Van Ngo ,  Paul R. Besser ,  Angela T. Hui

IPC分类号： H01L21336

CPC分类号： H01L29/665 ,  H01L21/31116

摘要： Sub-micron dimensioned, ultra-shallow junction MOS and/or CMOS transistor devices having reduced or minimal junction leakage are formed by a salicide process wherein carbonaceous residue on silicon substrate surfaces resulting from reactive plasma etching for sidewall spacer formation is removed prior to salicide processing. Embodiments include removing carbonaceous residues by performing a hydrogen ion plasma treatment.

摘要翻译： 通过自对准硅化物工艺形成具有减小的或最小的结泄漏的亚微米尺寸的超浅结MOS和/或CMOS晶体管器件，其中在自对准硅化物处理之前除去由用于侧壁间隔物形成的反应等离子体蚀刻而导致的硅衬底表面上的碳质残渣 。 实施方案包括通过进行氢离子等离子体处理来除去碳质残渣。

公开(公告)号：US06174743B1

公开(公告)日：2001-01-16

申请号：US09208623

申请日：1998-12-08

申请人： Suzette K. Pangrle ,  Paul R. Besser ,  Minh Van Ngo

发明人： Suzette K. Pangrle ,  Paul R. Besser ,  Minh Van Ngo

IPC分类号： H01L2131

CPC分类号： H01L21/3145 ,  H01L21/31612 ,  H01L21/76801

摘要： In a method for forming an interlayer dielectric (ILD) coating on microcircuit interconnect lines of a substrate, a SiON layer is formed by using plasma-enhanced chemical vapor deposition. The deposition using a plasma formed of nitrogen, nitrous oxide, and silane gases, with the gases being dispensed at regulated flow rates and being energized by a radio frequency power source. The plasma reacts to form SiON which is deposited on a semiconductor substrate. During deposition, silane flow rates are regulating and reducing to less than sixty standard cubic centimeters per minute, thereby reducing the incidence of stress-induced voiding in the underlying interconnect lines. During deposition adjustments are made in deposition temperature and process pressure to control the characteristics of the SiON layer. The SiON layer is tested for acceptable optical properties and acceptable SiON layers are coated with a SiO2 layer to complete formation of the ILD. Once the ILD is formed the substrate is in readiness for further processing.

摘要翻译： 在基板的微电路互连线上形成层间电介质（ILD）涂层的方法中，通过使用等离子体增强化学气相沉积形成SiON层。 使用由氮气，一氧化二氮和硅烷气体形成的等离子体的沉积，其中气体以稳定的流速分配并由射频电源激励。 等离子体反应形成沉积在半导体衬底上的SiON。 在沉积期间，硅烷流速调节并降低到每分钟少于六十标准立方厘米，从而降低底层互连线中应力引起的空隙的发生。 在淀积温度和工艺压力下进行沉积调整，以控制SiON层的特性。 测试SiON层的可接受的光学性能，并且用SiO 2层涂覆可接受的SiON层以完成ILD的形成。 一旦形成了ILD，底物就可以进行进一步的处理。