公开(公告)号：US06893910B1

公开(公告)日：2005-05-17

申请号：US10462670

申请日：2003-06-17

申请人： Christy Mei-Chu Woo ,  Paul R. Besser ,  Minh Van Ngo ,  James N. Pan ,  Jinsong Yin

发明人： Christy Mei-Chu Woo ,  Paul R. Besser ,  Minh Van Ngo ,  James N. Pan ,  Jinsong Yin

IPC分类号： H01L21/28 ,  H01L21/316 ,  H01L21/336 ,  H01L29/49 ,  H01L29/51 ,  H01L29/78 ,  H01L21/338 ,  H01L21/31 ,  H01L21/3205

CPC分类号： H01L21/28185 ,  H01L21/28079 ,  H01L21/28194 ,  H01L21/31683 ,  H01L29/4958 ,  H01L29/511 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66583 ,  H01L29/7833

摘要： A method for forming a semiconductor structure removes the temporary gate formed on the dielectric layer to expose a recess in which oxygen-rich CVD oxide is deposited. A tantalum layer is then deposited by low-power physical vapor deposition on the CVD oxide. Annealing is then performed to create a Ta2O5 region and a Ta region from the deposited oxide and Ta. This creates a low carbon-content Ta2O5 and a metallic Ta gate in a single process step.

摘要翻译： 用于形成半导体结构的方法去除形成在电介质层上的临时栅极以暴露其中沉积有富氧CVD氧化物的凹槽。 然后通过低功率物理气相沉积在CVD氧化物上沉积钽层。 然后进行退火以从沉积的氧化物和Ta形成Ta 2 O 5区域和Ta区域。 这在单一工艺步骤中产生低碳含量的Ta 2 O 5 O 5和金属Ta浇口。

公开(公告)号：US06861350B1

公开(公告)日：2005-03-01

申请号：US10464508

申请日：2003-06-19

申请人： Minh Van Ngo ,  Christy Mei-Chu Woo ,  Jinsong Yin ,  James Pan ,  Paul R. Besser

发明人： Minh Van Ngo ,  Christy Mei-Chu Woo ,  Jinsong Yin ,  James Pan ,  Paul R. Besser

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L29/49 ,  H10L21/4763 ,  H10L21/44

CPC分类号： H01L29/66606 ,  H01L21/28088 ,  H01L29/4966 ,  H01L29/66545

摘要： Micro-miniaturized semiconductor devices are fabricated with silicon-rich tantalum silicon nitride replacement metal gate electrodes. Embodiments include removing a removable gate, depositing a layer of tantalum nitride, as by PVD at a thickness of 25 Å to 75 Å, and then introducing silicon into the deposited tantalum nitride layer by thermal soaking in silane or silane plasma treatment to form a layer of silicon-rich tantalum silicon nitride. In another embodiment, the intermediate structure is subjected to thermal soaking in silane or silane plasma treatment before and after depositing the tantalum nitride layer. Embodiments further include pretreating the intermediate structure with silane prior to depositing the tantalum nitride layer, treating the deposited tantalum nitride layer with silane, and repeating these steps a number of times to form a plurality of sub-layers of silicon-rich tantalum silicon nitride.

摘要翻译： 微型半导体器件由富含硅的钽氮化硅替代金属栅电极制成。 实施例包括去除可移除栅极，通过PVD沉积氮化钽层，厚度为25埃，然后通过在硅烷或硅烷等离子体处理中热浸泡形成层，将硅引入沉积的氮化钽层中 的富硅钽硅氮化物。 在另一个实施方案中，在沉积氮化钽层之前和之后，使中间体在硅烷或硅烷等离子体处理中进行热浸。 实施例还包括在沉积氮化钽层之前用硅烷预处理中间结构，用硅烷处理沉积的氮化钽层，并重复这些步骤多次以形成多个富硅钽硅氮化物的子层。

公开(公告)号：US07033888B2

公开(公告)日：2006-04-25

申请号：US10806117

申请日：2004-03-23

申请人： James N. Pan ,  Paul R. Besser ,  Christy Woo ,  Minh Van Ngo ,  Jinsong Yin

发明人： James N. Pan ,  Paul R. Besser ,  Christy Woo ,  Minh Van Ngo ,  Jinsong Yin

IPC分类号： H01L21/336

CPC分类号： H01L29/66545 ,  H01L21/28088 ,  H01L29/4966

摘要： A metal gate electrode is formed with an intrinsic electric field to modify its work function and the threshold voltage of the transistor. Embodiments include forming an opening in a dielectric layer by removing a removable gate, depositing one or more layers of tantalum nitride such that the nitrogen content increases from the bottom of the layer adjacent the gate dielectric layer upwardly. Other embodiments include forming the intrinsic electric field to control the work function by doping one or more metal layers and forming metal alloys. Embodiments further include the use of barrier layers when forming metal gate electrodes.

摘要翻译： 形成具有固有电场的金属栅电极，以改变晶体管的功函数和阈值电压。 实施例包括通过去除可移除栅极来形成电介质层中的开口，沉积一层或多层氮化钽，使氮含量从邻近栅介质层的层的底部向上增加。 其他实施例包括通过掺杂一个或多个金属层并形成金属合金来形成本征电场以控制功函数。 实施例还包括在形成金属栅电极时使用阻挡层。

公开(公告)号：US06727560B1

公开(公告)日：2004-04-27

申请号：US10360719

申请日：2003-02-10

申请人： James N. Pan ,  Paul R. Besser ,  Christy Woo ,  Minh Van Ngo ,  Jinsong Yin

发明人： James N. Pan ,  Paul R. Besser ,  Christy Woo ,  Minh Van Ngo ,  Jinsong Yin

IPC分类号： H01L2976

CPC分类号： H01L29/66545 ,  H01L21/28088 ,  H01L29/4966

摘要： A metal gate electrode is formed with an intrinsic electric field to modify its work function and the threshold voltage of the transistor. Embodiments include forming an opening in a dielectric layer by removing a removable gate, depositing one or more layers of tantalum nitride such that the nitrogen content increases from the bottom of the layer adjacent the gate dielectric layer upwardly. Other embodiments include forming the intrinsic electric field to control the work function by doping one or more metal layers and forming metal alloys. Embodiments further include the use of barrier layers when forming metal gate electrodes.

公开(公告)号：US06661067B1

公开(公告)日：2003-12-09

申请号：US10260514

申请日：2002-10-01

申请人： Minh Van Ngo ,  Christy Mei-Chu Woo ,  Paul R. Besser ,  Robert A. Huertas

发明人： Minh Van Ngo ,  Christy Mei-Chu Woo ,  Paul R. Besser ,  Robert A. Huertas

IPC分类号： H01L2994

CPC分类号： H01L29/665 ,  H01L21/3115 ,  Y10S257/90

摘要： Bridging between nickel suicide layers on a gate electrode and source/drain regions along silicon nitride sidewall spacers is prevented by treating the exposed surfaces of the silicon nitride sidewall spacers with a nitrogen plasma to create a surface region having reduced free silicon. Embodiments include treating the silicon nitride sidewall spacers with a nitrogen plasma to reduce the refractive index of the surface region to less than about 1.95.

摘要翻译： 通过用氮等离子体处理氮化硅侧壁间隔物的暴露表面来形成具有减少的游离硅的表面区域，防止栅电极上的硅化镍层与沿着氮化硅侧壁间隔物的源/漏区之间的桥接。 实施例包括用氮等离子体处理氮化硅侧壁间隔物以将表面区域的折射率降低到小于约1.95。

公开(公告)号：US06605513B2

公开(公告)日：2003-08-12

申请号：US09729699

申请日：2000-12-06

申请人： Eric N. Paton ,  Ercan Adem ,  Jacques J. Bertrand ,  Paul R. Besser ,  Matthew S. Buynoski ,  John Clayton Foster ,  Paul L. King ,  George Jonathan Kluth ,  Minh Van Ngo ,  Christy Mei-Chu Woo

发明人： Eric N. Paton ,  Ercan Adem ,  Jacques J. Bertrand ,  Paul R. Besser ,  Matthew S. Buynoski ,  John Clayton Foster ,  Paul L. King ,  George Jonathan Kluth ,  Minh Van Ngo ,  Christy Mei-Chu Woo

IPC分类号： H01L21336

CPC分类号： H01L29/665 ,  H01L21/28061 ,  H01L21/28518 ,  H01L29/4933

摘要： A self-aligned silicide process that can accommodate a low thermal budget and form silicide regions of small dimensions in a controlled reaction. In a first temperature treatment, nickel metal or nickel alloy is reacted with a silicon material to form at least one high resistance nickel silicide region. Unreacted nickel is removed. A dielectric layer is then deposited over a high resistance nickel silicide regions. In a second temperature treatment, the at least one high resistance nickel silicide region and dielectric layer are reacted at a prescribed temperature to form at least one low resistance silicide region and process the dielectric layer. Bridging between regions is avoided by the two-step process as silicide growth is controlled, and unreacted nickel between silicide regions is removed after the first temperature treatment. The processing of the high resistance nickel silicide regions and the dielectric layer are conveniently combined into a single temperature treatment.

摘要翻译： 自对准硅化物工艺，可以适应低热预算，并在受控反应中形成小尺寸的硅化物区域。 在第一温度处理中，镍金属或镍合金与硅材料反应以形成至少一个高电阻镍硅化物区域。 去除未反应的镍。 然后将电介质层沉积在高电阻镍硅化物区域上。 在第二温度处理中，至少一个高电阻镍硅化物区域和电介质层在规定温度下反应以形成至少一个低电阻硅化物区域并处理介电层。 通过控制硅化物生长的两步法避免区域之间的桥接，并且在第一温度处理之后去除硅化物区域之间的未反应的镍。 将高电阻镍硅化物区域和电介质层的处理方便地组合成单温度处理。

公开(公告)号：US06465349B1

公开(公告)日：2002-10-15

申请号：US09679372

申请日：2000-10-05

申请人： Minh Van Ngo ,  Christy Mei-Chu Woo ,  Paul R. Besser ,  Robert A. Huertas

发明人： Minh Van Ngo ,  Christy Mei-Chu Woo ,  Paul R. Besser ,  Robert A. Huertas

IPC分类号： H01L2144

CPC分类号： H01L29/665 ,  H01L21/3115 ,  Y10S257/90

摘要： Bridging between nickel silicide layers on a gate electrode and source/drain regions along silicon nitride sidewall spacers is prevented by treating the exposed surfaces of the silicon nitride sidewall spacers with a nitrogen plasma to create a surface region having reduced free silicon. Embodiments include treating the silicon nitride sidewall spacers with a nitrogen plasma to reduce the refractive index of the surface region to less than about 1.95.

摘要翻译： 通过用氮等离子体处理氮化硅侧壁间隔物的暴露表面以形成具有减少的自由硅的表面区域，防止沿栅极电极的硅化镍层与氮化硅侧壁间隔物的源极/漏极区之间的桥接。 实施例包括用氮等离子体处理氮化硅侧壁间隔物以将表面区域的折射率降低到小于约1.95。

公开(公告)号：US06545370B1

公开(公告)日：2003-04-08

申请号：US09679375

申请日：2000-10-05

申请人： Minh Van Ngo ,  Christy Mei-Chu Woo ,  Paul R. Besser

发明人： Minh Van Ngo ,  Christy Mei-Chu Woo ,  Paul R. Besser

IPC分类号： H01L27088

CPC分类号： H01L29/665 ,  H01L29/4983 ,  H01L29/6656

摘要： Bridging between nickel silicide layers on a gate electrode and source/drain regions along silicon nitride sidewall spacers is prevented by employing composite silicon nitride sidewall spacers comprising an outer layer having reduced free silicon. Embodiments include forming composite silicon nitride sidewall spacers comprising an inner silicon nitride layer, having a refractive index of about 1.95 to about 2.05 and a thickness of about 450 Å to about 550 Å, on the side surfaces of the gate electrode and an outer silicon nitride layer, having a refractive index to less than about 1.95 and a thickness of about 350 Å to about 450 Å.

摘要翻译： 通过使用复合氮化硅侧壁间隔物来防止在栅电极上的硅化镍层和沿着氮化硅侧壁间隔物的源极/漏极区之间的桥接，所述复合氮化硅侧壁间隔物包括具有减少的自由硅的外层。 实施例包括形成复合氮化硅侧壁间隔物，其包括内部氮化硅层，折射率为约1.95至约2.05，厚度约为450至大约的厚度在栅电极和外部氮化硅 层，具有小于约1.95的折射率和约350至约的厚度。

公开(公告)号：US06372673B1

公开(公告)日：2002-04-16

申请号：US09781256

申请日：2001-02-13

申请人： Paul R. Besser ,  Minh Van Ngo ,  Christy Mei-Chu Woo ,  George Jonathan Kluth

发明人： Paul R. Besser ,  Minh Van Ngo ,  Christy Mei-Chu Woo ,  George Jonathan Kluth

IPC分类号： H01L21318

CPC分类号： H01L29/665 ,  H01L21/3185

摘要： Bridging between a metal silicide e.g., nickel silicide, layer on a gate electrode and metal silicide layers on associated source/drain regions is avoided by forming silicon-starved silicon nitride sidewall spacers having substantially no or significantly reduced Si available for reaction with deposited metal, e.g., nickel.

摘要翻译： 通过形成具有基本上没有或显着减少的Si的硅绝缘氮化硅侧壁间隔物来避免金属硅化物（例如，硅化镍），栅极上的层和相关源极/漏极区域上的金属硅化物层之间的桥接，可用于与沉积金属反应， 例如镍。

公开(公告)号：US06387767B1

公开(公告)日：2002-05-14

申请号：US09781448

申请日：2001-02-13

申请人： Paul R. Besser ,  Minh Van Ngo ,  Christy Mei-Chu Woo ,  George Jonathan Kluth

发明人： Paul R. Besser ,  Minh Van Ngo ,  Christy Mei-Chu Woo ,  George Jonathan Kluth

IPC分类号： H01L21336

CPC分类号： H01L29/665

摘要： Salicide processing is implemented with nitrogen-rich silicon nitride sidewall spacers that allow a metal silicide layer e.g., NiSi, to be formed over the polysilicon gate electrode and source/drain regions using salicide technology without associated bridging between the metal silicide layer on the gate electrode and the metal silicide layers over the source/drain regions. Bridging between a metal silicide e.g., nickel silicide, layer on a gate electrode and metal silicide layers on associated source/drain regions is avoided by forming nitrogen-rich silicon nitride sidewall spacers with increased nitrogen, thereby eliminating free Si available to react with the metal subsequently deposited and thus avoiding the formation of metal silicide on the sidewall spacers.

摘要翻译： 使用富含氮的氮化硅侧壁间隔物实现自杀处理，其允许使用硅化物技术在多晶硅栅极电极和源极/漏极区域上形成金属硅化物层，例如NiSi，而不会在栅极上的金属硅化物层之间相互桥接 和源极/漏极区域之间的金属硅化物层。通过形成具有增加的富氮氮化硅侧壁间隔物，避免了金属硅化物（例如，硅化镍），栅极上的层和相关源极/漏极区域上的金属硅化物层之间的结合 氮，从而消除可用于随后沉积的金属的游离Si，从而避免在侧壁间隔物上形成金属硅化物。