公开(公告)号：US5665991A

公开(公告)日：1997-09-09

申请号：US456238

申请日：1995-05-31

申请人： Taylor R. Efland ,  Satwinder Malhi ,  Michael C. Smayling ,  Joseph A. Devore ,  Ross E. Teggatz ,  Alec J. Morton

发明人： Taylor R. Efland ,  Satwinder Malhi ,  Michael C. Smayling ,  Joseph A. Devore ,  Ross E. Teggatz ,  Alec J. Morton

IPC分类号： H01L23/482 ,  H01L23/528 ,  H01L29/417 ,  H01L29/78 ,  H01L23/522

CPC分类号： H01L23/5286 ,  H01L23/4824 ,  H01L29/41725 ,  H01L29/41758 ,  H01L29/7816 ,  H01L29/7835 ,  H01L2924/0002

摘要： The device has a semiconductor chip having active circuitry in the face thereof. The circuitry has busing over it containing two conductive layers having a plurality of contacts and vias with spacings between them that alternate with respect to one another to provide current ballasting and improved switching uniformity. The spacings between the alternating contacts and vias provide regions of maximum conductor thickness and therefore reduces the busing resistance. Staggering the rows of alternating contacts and vias provides further current ballasting. A first conducting layer is used to contact and provide electrically isolated low resistive conducting paths to the various semiconductor regions while the second conducting region is used to provide selective contact to the first conductive layer, thus providing a means of busing large currents over active semiconductor area without sacrificing performance parameters.

摘要翻译： 该器件具有在其表面上具有有源电路的半导体芯片。 该电路具有引线，其中包含两个具有多个触点的导电层和在它们之间具有相互间交替的间隙的通孔，以提供电流镇流和改善的开关均匀性。 交替触点和通孔之间的间距提供最大导体厚度的区域，因此降低了阻抗。 交错的交替触点和通孔的排列提供了进一步的电流镇流。 第一导电层用于接触并提供到各种半导体区域的电隔离的低电阻导电路径，而第二导电区域用于提供与第一导电层的选择性接触，从而提供在有源半导体区域上引入大电流的装置 而不牺牲性能参数。

公开(公告)号：US5640034A

公开(公告)日：1997-06-17

申请号：US883985

申请日：1992-05-18

申请人： Satwinder Malhi

发明人： Satwinder Malhi

IPC分类号： H01L21/336 ,  H01L29/423 ,  H01L29/78 ,  H01L29/76 ,  H01L29/94

CPC分类号： H01L29/7809 ,  H01L29/42368 ,  H01L29/7813 ,  H01L29/7834

摘要： A top drain trench based RESURF DMOS (reduced surface field double diffused MOS) transistor structure provides improved RDSon performance by minimizing transistor cell pitch. The transistor includes a gate, a source and drain. The trench may include a nonuniform dielectric lining. A drain drift region partially surrounds the trench. Current flows laterally enabling multiple trench based RESURF DMOS transistors to be formed on a single semiconductor die. The addition of an isolation region to electrically isolate the source from the substrate allows the power transistor to be incorporated into high side driver applications as well as other application mandating electrical isolation between the source and ground.

摘要翻译： 基于顶漏沟槽的RESURF DMOS（减小的表面场双扩散MOS）晶体管结构通过最小化晶体管单元间距来提供改善的RDSon性能。 晶体管包括栅极，源极和漏极。 沟槽可以包括不均匀的电介质衬里。 漏极漂移区域部分地围绕沟槽。 电流横向流动，使得能够在单个半导体管芯上形成多个基于沟槽的RESURF DMOS晶体管。 添加隔离区以将源极与衬底电隔离允许将功率晶体管并入高侧驱动器应用以及强制源极和地之间的电隔离的其他应用。

公开(公告)号：US5486484A

公开(公告)日：1996-01-23

申请号：US255023

申请日：1994-07-25

申请人： Satwinder Malhi

发明人： Satwinder Malhi

IPC分类号： H01L29/78 ,  H01L27/06 ,  H01L29/24 ,  H01L29/423 ,  H01L21/443

CPC分类号： H01L29/1608 ,  H01L27/0605 ,  H01L29/42368 ,  Y10S438/931

摘要： A MOSFET device (100) having a silicon carbide substrate (102). A channel region (106) of a first conductivity type and an epitaxial layer (104) of a second conductivity type are located above the silicon carbide substrate (102). First and second source/drain regions (118), also of the first conductivity type are located directly within the channel region (106). No well region is placed between the first and second source/drain regions (118) and the channel region (106). A gate (120) is separated from the channel region (106) by an insulator layer (110). Insulator layer (110) has a thin portion (114) and a thick portion (116).

公开(公告)号：US5349207A

公开(公告)日：1994-09-20

申请号：US20820

申请日：1993-02-22

申请人： Satwinder Malhi

发明人： Satwinder Malhi

IPC分类号： H01L21/20 ,  H01L21/762 ,  H01L29/10 ,  H01L29/24 ,  H01L29/786 ,  H01L29/161

CPC分类号： H01L29/1608 ,  H01L21/2007 ,  H01L21/762 ,  H01L29/1079 ,  H01L29/78684 ,  Y10S148/148 ,  Y10S438/931

摘要： A silicon carbide structure (10) and method capable of using existing silicon wafer fabrication facilities. A silicon wafer (20) is provided which has a first diameter. At least one silicon carbide wafer (30) is provided which has a given width and length (or diameter). The width and length (or diameter) of the silicon carbide wafer (30) are smaller than the diameter of the silicon wafer (20). The silicon wafer (20) and the silicon carbide wafer (30) are then bonded together. The bonding layer (58) may comprise silicon germanium, silicon dioxide, silicate glass or other materials. Structures such as MOSFET (62) may be then formed in silicon carbide wafer (30).

摘要翻译： 一种能够使用现有的硅晶片制造设备的碳化硅结构（10）和方法。 提供具有第一直径的硅晶片（20）。 提供至少一个具有给定宽度和长度（或直径）的碳化硅晶片（30）。 碳化硅晶片（30）的宽度和长度（或直径）小于硅晶片（20）的直径。 然后将硅晶片（20）和碳化硅晶片（30）接合在一起。 结合层（58）可以包括硅锗，二氧化硅，硅酸盐玻璃或其它材料。 然后可以在碳化硅晶片（30）中形成诸如MOSFET（62）的结构。

公开(公告)号：US5172208A

公开(公告)日：1992-12-15

申请号：US722376

申请日：1991-06-25

申请人： Satwinder Malhi

发明人： Satwinder Malhi

IPC分类号： H01L29/74 ,  H01L29/745

CPC分类号： H01L29/7455 ,  H01L29/7436

摘要： A thyristor (38) is formed over an insulating layer (44). A gate (70) is operable to create a depletion region through the semiconductor layer (46) in which the thyristor (38) is implemented in order to turn the thyristor off. Isolation regions (48, 52) prevent operation of the thyristor from affecting adjacent devices.

摘要翻译： 在绝缘层（44）上形成晶闸管（38）。 栅极（70）可操作以通过其中实施晶闸管（38）的半导体层（46）产生耗尽区，以便关断晶闸管。 隔离区域（48,52）防止晶闸管的操作影响相邻的设备。

公开(公告)号：US5933320A

公开(公告)日：1999-08-03

申请号：US771178

申请日：1996-12-20

申请人： Satwinder Malhi

发明人： Satwinder Malhi

IPC分类号： G06F1/16 ,  G06F3/02 ,  H01H13/14

CPC分类号： G06F3/0221 ,  G06F1/1616 ,  G06F1/1666 ,  H01H2223/052

摘要： A notebook computer (10) including a keyboard (14) having gas or piston expandable keys (18) which may be placed in an expanded or compressed state. While in an expanded state, the keys (18) are approximately the size of the keys on a standard keyboard. While in a compressed state, the keys are essentially flat, allowing the keyboard to be folded upon itself. Accordingly, the keyboard (18) may be folded in a compressed state when the computer is not in use to reduce keyboard area, and unfolded and expanded to provide a full size keyboard when the computer is in use.

摘要翻译： 一种笔记本计算机（10），包括具有气体或活塞可扩张键（18）的键盘（14），所述钥匙可以放置在膨胀或压缩状态。 在扩展状态下，键（18）大约是标准键盘上的键的大小。 在处于压缩状态时，键基本上是平的，允许键盘折叠在自身上。 因此，当计算机不使用以减少键盘区域时，键盘（18）可以被折叠成压缩状态，并且在计算机使用时展开并扩展以提供全尺寸键盘。

公开(公告)号：US5539238A

公开(公告)日：1996-07-23

申请号：US939349

申请日：1992-09-02

申请人： Satwinder Malhi

发明人： Satwinder Malhi

IPC分类号： H01L21/316 ,  H01L21/225 ,  H01L21/336 ,  H01L21/76 ,  H01L29/06 ,  H01L29/08 ,  H01L29/417 ,  H01L29/78 ,  H01L29/00 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062

CPC分类号： H01L29/7835 ,  H01L29/0615 ,  H01L29/0653 ,  H01L29/66636 ,  H01L29/66659 ,  H01L29/7809 ,  H01L29/7816 ,  H01L29/7834 ,  H01L21/2255 ,  H01L29/0847 ,  H01L29/41766 ,  Y10S148/126

摘要： A high voltage power transistor cell is developed that provides improved RDSon performance without sacrificing breakdown performance through utilization of trench based transistor technology. A source, drain and trench are formed within a substrate. A gate is formed on the surface over a spacing between the source and the trench. A drift region is formed around the trench. An isolation region may optionally be added allowing electrical isolation between the source and the substrate. The lateral current flow feature allows multiple high voltage power transistors, electrically isolated from one another, to exist on a single semiconductor chip. The drift region formed around the trench provides RESURF transistor characteristics without sacrificing die area.

摘要翻译： 开发了一种高电压功率晶体管单元，通过利用基于沟槽的晶体管技术，可以提供更好的RDSon性能，而不会牺牲击穿性能。 在衬底内形成源极，漏极和沟槽。 在源极和沟槽之间的间隔上的表面上形成栅极。 在沟槽周围形成漂移区域。 可以可选地添加隔离区域，允许源极和衬底之间的电隔离。 横向电流流动特征允许在单个半导体芯片上存在彼此电隔离的多个高压功率晶体管。 围绕沟槽形成的漂移区域提供RESURF晶体管特性，而不牺牲管芯面积。

公开(公告)号：US5532957A

公开(公告)日：1996-07-02

申请号：US381180

申请日：1995-01-31

申请人： Satwinder Malhi

发明人： Satwinder Malhi

IPC分类号： G11C11/41 ,  G11C11/412 ,  H03K3/356 ,  H03K19/173 ,  G11C11/00

CPC分类号： H03K19/1736 ,  G11C11/41 ,  G11C11/412 ,  H03K3/356104

摘要： All of the components of a standard logic gate wherein high precision is required, preferably a NAND gate, are provided, preferably in bulk silicon and the remaining components required for a memory cell wherein relatively low precision is required, preferably an SRAM, as well as a mode select circuit are provided, preferably in a polysilicon layer over the bulk silicon. The mode select circuit is design to operate in plural modes, a two mode mode select circuit being the preferred embodiment. In any mode of operation as determined by the mode select circuit, all unused or unrequired circuitry is either isolated from the active portion of the circuit or used to enhance operation of required circuitry, such as, for example, operating in parallel therewith or in series therewith. The polysilicon layer, if used, can be disposed over the bulk silicon with vias and interconnects therebetween. The resulting circuit can require less circuit area required by a similar prior art circuits of both of the configurations obtainable, yet be capable of providing any one of plural selected functions. In addition, the improved hardware utilization is conducive to speed enhancement and lower power utilization due to paralleling.

摘要翻译： 优选地，在体硅中提供需要高精度的标准逻辑门的所有组件，优选地是NAND门，以及需要相对较低精度的存储单元所需的其余部件，优选为SRAM，以及 提供模式选择电路，优选地在体硅上的多晶硅层中。 模式选择电路设计为以多种模式操作，双模式模式选择电路是优选实施例。 在由模式选择电路确定的任何操作模式中，所有未使用或不需要的电路与电路的有源部分隔离或用于增强所需电路的操作，例如与其并联或串联操作 随之而来。 如果使用多晶硅层，则可以在体硅之间设置通孔和它们之间的互连。 所得到的电路可以要求较少的两个可获得的配置的现有技术电路所需的电路面积，但是能够提供多个选定功能中的任何一个。 此外，改进的硬件利用率有利于速度提高，并且由于并联而降低功率利用率。

公开(公告)号：US5525814A

公开(公告)日：1996-06-11

申请号：US375143

申请日：1995-01-19

申请人： Satwinder Malhi

发明人： Satwinder Malhi

IPC分类号： G06F7/00 ,  H01L21/8234 ,  H01L27/00 ,  H01L27/06 ,  H01L27/088 ,  H01L27/118 ,  H01L29/786 ,  H01L27/11

CPC分类号： H01L27/0688 ,  H01L27/11803 ,  Y10S257/903

摘要： A three dimensional latch and bulk silicon pass transistor for high density field reconfigurable architectures is provided utilizing bulk silicon with a layer of polysilicon or silicon on insulator (SOI) thereover. The pass transistor, which must have very low resistance to provide a good short circuit path between the metal runs and fast switching speed, is fabricated in the bulk silicon wherein the resistivity can be made very low relative to polysilicon and because only the pass transistor is disposed in the bulk silicon, thereby permitting the dimensions thereof to be increased to provide even lower resistance. Since only the latch is fabricated in the layer of polysilicon or SOI and is disposed over the pass transistor, the amount of chip area utilized can be the same or less than required in the prior art wherein all circuitry was in the bulk silicon. While the resistivity in the polysilicon will be higher than in the bulk silicon, the latch can operate adequately under such conditions of high resistivity since high speed operation thereof is not of importance in the environment in question. The very low resistance path of the pass transistor allows for faster response time than can be obtained in polysilicon for reconfiguration operations.

摘要翻译： 提供了一种用于高密度场可重构架构的三维闩锁和体硅传输晶体管，其利用具有多晶硅层或绝缘体上硅（SOI））的体硅。 在体硅中制造必须具有非常低的电阻以提供金属行之间的良好的短路路径和快速切换速度的传输晶体管，其中相对于多晶硅可以使电阻率非常低，并且因为只有通过晶体管是 设置在体硅中，从而允许其尺寸增加以提供甚至更低的电阻。 由于仅在多晶硅或SOI层中制造锁存器并且设置在通过晶体管上方，所使用的芯片面积的量可以与现有技术中所需的芯片面积相同或更小，其中所有电路都在体硅中。 虽然多晶硅中的电阻率将高于体硅中的电阻率，但是在高电阻率的这种条件下，闩锁可以充分运行，因为其高速运行在所讨论的环境中不重要。 传输晶体管的非常低的电阻路径允许比用于重新配置操作的多晶硅可以获得更快的响应时间。

公开(公告)号：US5512495A

公开(公告)日：1996-04-30

申请号：US390269

申请日：1995-02-16

申请人： Chia-Cu P. Mei ,  Satwinder Malhi

发明人： Chia-Cu P. Mei ,  Satwinder Malhi

IPC分类号： H01L21/336 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/78 ,  H01L21/266

CPC分类号： H01L29/66659 ,  H01L29/0847 ,  H01L29/42368 ,  H01L29/7835 ,  Y10S148/126

摘要： A high voltage PMOS transistor 7 has improved on resistance by adjusting impurity concentration in a lightly doped drift region rim 48 to compensate for impurity segregation which occurs during the growth phase of a thick field oxide 43. During fabrication of high voltage PMOS device 7, a shallow vertical junction 230 formed by impurity segregation into field oxide 43. Implanting an HV drift region p-tank rim adjustment 220 and annealing it forms a lateral junction 250 and isolates the shallow junction 230 under field oxide 43. Thereby, the on-resistance of high voltage PMOS transistor 7 is minimized.

摘要翻译： 高电压PMOS晶体管7通过调整轻掺杂漂移区边缘48中的杂质浓度来改善导通电阻，以补偿在厚场氧化物43的生长阶段期间发生的杂质偏析。在制造高电压PMOS器件7期间， 通过杂质偏析形成场氧化物43形成的浅垂直结230.注入HV漂移区域p型槽边缘调节件220并进行退火形成横向接合部250，并将浅结230隔离在场氧化物43下。由此，导通电阻 高电压PMOS晶体管7最小化。