公开(公告)号：US20150039938A1

公开(公告)日：2015-02-05

申请号：US14486776

申请日：2014-09-15

Applicant: ORACLE INTERNATIONAL CORPORATION

Inventor： Ramaswamy Sivaramakrishnan ,  Ali Vahidsafa ,  Aaron S. Wynn ,  Connie W. Cheung

IPC: G06F11/07 ,  G06F12/08

CPC classification number: G06F11/0793 ,  G06F9/30 ,  G06F9/30047 ,  G06F11/073 ,  G06F11/1666 ,  G06F11/20 ,  G06F12/0804 ,  G06F12/0844 ,  G06F12/0891 ,  G06F12/126 ,  G06F2212/1008 ,  G06F2212/1032

Abstract: The systems and methods described herein may provide a flush-retire instruction for retiring “bad” cache locations (e.g., locations associated with persistent errors) to prevent their allocation for any further accesses, and a flush-unretire instruction for unretiring cache locations previously retired. These instructions may be implemented as hardware instructions of a processor. They may be executable by processes executing in a hyper-privileged state, without the need to quiesce any other processes. The flush-retire instruction may atomically flush a cache line implicated by a detected cache error and set a lock bit to disable subsequent allocation of the corresponding cache location. The flush-unretire instruction may atomically flush an identified cache line (if valid) and clear the lock bit to re-enable subsequent allocation of the cache location. Various bits in the encodings of these instructions may identify the cache location to be retired or unretired in terms of the physical cache structure.

Abstract translation: 本文描述的系统和方法可以提供用于退出“不良”高速缓存位置（例如，与持续错误相关联的位置）的刷新退出指令，以防止其对任何进一步访问的分配，以及用于撤销先前退休的高速缓存位置的刷新指令 。 这些指令可以被实现为处理器的硬件指令。 它们可以由以超级特权状态执行的进程执行，而不需要使任何其他进程停顿。 刷新 - 退出指令可以原子地刷新由检测到的高速缓存错误所牵连的高速缓存行，并设置锁定位以禁用对应的高速缓存位置的后续分配。 flush-unretire指令可以原子地刷新已识别的高速缓存行（如果有效）并清除锁定位以重新启用高速缓存位置的后续分配。 这些指令的编码中的各个比特可以根据物理高速缓存结构来标识要退休或未退出的高速缓存位置。

公开(公告)号：US08904254B2

公开(公告)日：2014-12-02

申请号：US13673503

申请日：2012-11-09

Applicant: Oracle International Corporation

Inventor： Robert P. Masleid ,  Ali Vahidsafa

IPC: G01R31/28

CPC classification number: G01R31/318541

Abstract: A combo dynamic flop with scan flop circuit includes a flip-flop circuit, a scan control circuit, and an output buffer circuit. The flip-flop circuit includes a dynamic latch circuit and a static latch circuit. The dynamic latch circuit includes a dynamic latch storage node. The static latch circuit includes a static storage node driven by the dynamic latch. The scan control circuit includes a scan slave feed-forward circuit, a scan latch circuit, and a scan driver circuit driven by the scan feed-back circuit. The scan latch circuit includes a scan feed-back circuit, a scan storage node, and a scan feed-forward circuit driven from the static latch. The output buffer circuit includes a dynamic latch driver driven from the dynamic latch circuit and a static driver driven from the static latch circuit.

Abstract translation: 具有扫描电路的组合动态触发器包括触发器电路，扫描控制电路和输出缓冲电路。 触发器电路包括动态锁存电路和静态锁存电路。 动态锁存电路包括动态锁存存储节点。 静态锁存电路包括由动态锁存器驱动的静态存储节点。 扫描控制电路包括扫描从机前馈电路，扫描锁存电路和由扫描反馈电路驱动的扫描驱动电路。 扫描锁存电路包括扫描反馈电路，扫描存储节点和从静态锁存器驱动的扫描前馈电路。 输出缓冲电路包括从动态锁存电路驱动的动态锁存驱动器和从静态锁存电路驱动的静态驱动器。

公开(公告)号：US20140210526A1

公开(公告)日：2014-07-31

申请号：US13755056

申请日：2013-01-31

Applicant: ORACLE INTERNATIONAL CORPORATION

Inventor： Robert P. Masleid ,  Ali Vahidsafa

IPC: H03L7/00

CPC classification number: H03L7/00 ,  H04L7/005 ,  H04L7/02 ,  H04L25/05

Abstract: A rotational synchronizer for metastability resolution is disclosed. A synchronizer includes a plurality of M+1 latches each coupled to receive data through a common data input. The synchronizer further includes a multiplexer having a N inputs each coupled to receive data from an output of a corresponding one of the M+1 latches, and an output, wherein the multiplexer is configured to select one of its inputs to be coupled to the output. A control circuit is configured to cause the multiplexer to sequentially select outputs of the M+1 latches responsive to N successive clock pulses, and further configured to cause the M+1 latches to sequentially latch data received through the common data input.

Abstract translation: 公开了一种用于亚稳定性分辨率的旋转同步器。 同步器包括多个M + 1个锁存器，每个锁存器被耦合以通过公共数据输入来接收数据。 所述同步器还包括多路复用器，其具有N个输入端，每个输入端分别被耦合以从所述M + 1锁存器中对应的一个锁存器的输出端接收数据，以及输出端，其中，所述多路复用器被配置为选择其输入之一耦合到所述输出端 。 控制电路被配置为使得多路复用器响应于N个连续时钟脉冲顺序地选择M + 1个锁存器的输出，并且还被配置为使得M + 1锁存器顺序地锁存通过公共数据输入接收到的数据。

公开(公告)号：US11709742B2

公开(公告)日：2023-07-25

申请号：US17648443

申请日：2022-02-02

Applicant: Oracle International Corporation

Inventor： James Lewis ,  Paul Jordan ,  Gregory Onufer ,  Ali Vahidsafa

IPC: G06F11/00 ,  G06F11/20 ,  G06F9/30 ,  G06F12/0875 ,  G06F12/0815 ,  G06F12/1027 ,  G06F9/38 ,  G06F9/48 ,  G06F3/06

CPC classification number: G06F11/2028 ,  G06F3/0617 ,  G06F3/0647 ,  G06F3/0683 ,  G06F9/30145 ,  G06F9/3851 ,  G06F9/3861 ,  G06F9/485 ,  G06F12/0815 ,  G06F12/0875 ,  G06F12/1027 ,  G06F2201/805 ,  G06F2212/452 ,  Y02D10/00

Abstract: An apparatus is disclosed in which the apparatus may include a plurality of cores, including a first core, a second core and a third core, and circuitry coupled to the first core. The first core may be configured to process a plurality of instructions. The circuitry may be may be configured to detect that the first core stopped committing a subset of the plurality of instructions, and to send an indication to the second core that the first core stopped committing the subset. The second core may be configured to disable the first core from further processing instructions of the subset responsive to receiving the indication, and to copy data from the first core to a third core responsive to disabling the first core. The third core may be configured to resume processing the subset dependent upon the data.

公开(公告)号：US20200210185A1

公开(公告)日：2020-07-02

申请号：US16735564

申请日：2020-01-06

Applicant: Oracle International Corporation

Inventor： James Lewis ,  Paul Jordan ,  Gregory Onufer ,  Ali Vahidsafa

IPC: G06F9/30 ,  G06F12/0875 ,  G06F12/0815 ,  G06F12/1027 ,  G06F9/38 ,  G06F9/48 ,  G06F3/06 ,  G06F11/20

Abstract: An apparatus is disclosed in which the apparatus may include a plurality of cores, including a first core, a second core and a third core, and circuitry coupled to the first core. The first core may be configured to process a plurality of instructions. The circuitry may be may be configured to detect that the first core stopped committing a subset of the plurality of instructions, and to send an indication to the second core that the first core stopped committing the subset. The second core may be configured to disable the first core from further processing instructions of the subset responsive to receiving the indication, and to copy data from the first core to a third core responsive to disabling the first core. The third core may be configured to resume processing the subset dependent upon the data.

公开(公告)号：US10656205B2

公开(公告)日：2020-05-19

申请号：US15886566

申请日：2018-02-01

Applicant: Oracle International Corporation

Inventor： Mark Semmelmeyer ,  Ali Vahidsafa ,  Sebastian Turullols ,  Scott Cooke ,  Senthilkumar Diraviam ,  Preethi Sama

IPC: G01R31/3183 ,  G01R31/28 ,  G01R31/319 ,  G01R31/317

Abstract: Embodiments include systems and methods for in-system, scan-based device testing using novel narrow-parallel (NarPar) implementations. Embodiments include a virtual automated test environment (VATE) system that can be disposed within the operating environment of an integrated circuit for which scan-based testing is desired (e.g., a chip under test, or CuT). For example, the VATE system is coupled with a service processor and with the CuT via a novel NarPar interface. A sequence controller can drive a narrow set of parallel scan pins on the CuT via the NarPar interface of the VATE system in accordance with an adapted test sequence having bit vector stimulants and expected responses. Responses of the CuT to the bit vector stimulants can be read out and compared to the expected results for scan-based testing of the chip.

公开(公告)号：US09645903B2

公开(公告)日：2017-05-09

申请号：US14675271

申请日：2015-03-31

Applicant: Oracle International Corporation

Inventor： Ali Vahidsafa ,  Connie Wai Mun Cheung

IPC: G06F11/00 ,  G06F11/20 ,  G06F12/1036 ,  G06F3/06 ,  G06F12/06

CPC classification number: G06F11/2094 ,  G06F3/0647 ,  G06F11/141 ,  G06F11/20 ,  G06F11/2069 ,  G06F12/0646 ,  G06F12/1036 ,  G06F2212/656

Abstract: A method for managing a failed memory module, including: receiving a first request to access a first memory address; identifying a memory module identifier (ID) from an end bit segment of the first memory address in the first request; generating, based on the memory module ID matching the failed memory module, a first revised memory address from the first memory address; and sending the first request with the first revised memory address to a memory controller for interpretation.

公开(公告)号：US20170091059A1

公开(公告)日：2017-03-30

申请号：US15202308

申请日：2016-07-05

Applicant: Oracle International Corporation

Inventor： Ali Vahidsafa

IPC: G06F11/27 ,  G06F11/25

CPC classification number: G06F11/25

Abstract: Implementations of the present disclosure involve an apparatus and/or method for conducting an at-speed functional test on a silicon wafer of an integrated circuit. In one embodiment, the method includes utilizing a first clock signal during a first portion of the test and a second clock signal during a second portion. The clock signals are configured such that a first subset of the logic stages of the circuit are tested at-speed by the first portion and a second subset of the logic stages of the circuit are tested at-speed. Further, in one embodiment, the first subset and the second subset comprise all of the logic stages of the circuit design. Through the configuration of the clock signals, the tester may ensure that each stage of the circuit design is tested at-speed such that a more accurate at-speed test result may be obtained in a low current environment.

公开(公告)号：US09569322B2

公开(公告)日：2017-02-14

申请号：US14675376

申请日：2015-03-31

Applicant: Oracle International Corporation

Inventor： Ali Vahidsafa ,  Connie Wai Mun Cheung

IPC: G06F12/00 ,  G06F11/20 ,  G06F12/10 ,  G06F3/06 ,  G06F12/06

CPC classification number: G06F11/2094 ,  G06F3/0647 ,  G06F11/141 ,  G06F11/20 ,  G06F11/2069 ,  G06F12/0646 ,  G06F12/1036 ,  G06F2212/656

Abstract: A method for memory migration between addressing schemes, including: receiving a first request to access a first memory address and a second request to access a second memory address; comparing the first memory address and the second memory address with a barrier pointer referencing a barrier address and separating migrated addresses and un-migrated addresses; tagging the first request with a first tag indicative of the first addressing scheme in response to the first memory address being on an un-migrated side of the barrier address; tagging the second request with a second tag indicative of the second addressing scheme in response to the second memory address being on a migrated side of the barrier address; and sending the first request to a first memory controller unit (MCU) and the second request to a second MCU.

Abstract translation: 一种用于寻址方案之间的存储器迁移的方法，包括：接收访问第一存储器地址的第一请求和访问第二存储器地址的第二请求; 将第一存储器地址和第二存储器地址与引用屏障地址的屏障指针进行比较，并分离迁移的地址和未迁移的地址; 响应于所述第一存储器地址位于所述屏障地址的未迁移侧，用指示所述第一寻址方案的第一标签来标记所述第一请求; 响应于所述第二存储器地址位于所述屏障地址的迁移侧，用指示所述第二寻址方案的第二标签来标记所述第二请求; 并将第一请求发送到第一存储器控制器单元（MCU），并将第二请求发送到第二MCU。

公开(公告)号：US20150278109A1

公开(公告)日：2015-10-01

申请号：US14675376

申请日：2015-03-31

Applicant: Oracle International Corporation

Inventor： Ali Vahidsafa ,  Connie Wai Mun Cheung

IPC: G06F12/10

CPC classification number: G06F11/2094 ,  G06F3/0647 ,  G06F11/141 ,  G06F11/20 ,  G06F11/2069 ,  G06F12/0646 ,  G06F12/1036 ,  G06F2212/656

Abstract: A method for memory migration between addressing schemes, including: receiving a first request to access a first memory address and a second request to access a second memory address; comparing the first memory address and the second memory address with a barrier pointer referencing a barrier address and separating migrated addresses and un-migrated addresses; tagging the first request with a first tag indicative of the first addressing scheme in response to the first memory address being on an un-migrated side of the barrier address; tagging the second request with a second tag indicative of the second addressing scheme in response to the second memory address being on a migrated side of the barrier address; and sending the first request to a first memory controller unit (MCU) and the second request to a second MCU.

Abstract translation: 一种用于寻址方案之间的存储器迁移的方法，包括：接收访问第一存储器地址的第一请求和访问第二存储器地址的第二请求; 将第一存储器地址和第二存储器地址与引用屏障地址的屏障指针进行比较，并分离迁移的地址和未迁移的地址; 响应于所述第一存储器地址位于所述屏障地址的未迁移侧，用指示所述第一寻址方案的第一标签来标记所述第一请求; 响应于所述第二存储器地址位于所述屏障地址的迁移侧，用指示所述第二寻址方案的第二标签来标记所述第二请求; 并将第一请求发送到第一存储器控制器单元（MCU），并将第二请求发送到第二MCU。