公开(公告)号：US20140206105A1

公开(公告)日：2014-07-24

申请号：US14221324

申请日：2014-03-21

Applicant: QUALCOMM Incorporated

Inventor： Jonghae Kim ,  Feng Wang ,  Matthew Michael Nowak

IPC: H01L49/02 ,  H01L23/522

CPC classification number: H01L28/10 ,  H01F27/2804 ,  H01L21/50 ,  H01L23/5227 ,  H01L23/645 ,  H01L23/66 ,  H01L24/48 ,  H01L2223/6644 ,  H01L2223/6655 ,  H01L2224/16 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/00014 ,  H01L2924/1305 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/19015 ,  H01L2924/19041 ,  H01L2924/19103 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: Methods for transformer signal coupling and impedance matching for flip-chip circuit assemblies are presented. In one embodiment, a method for providing an inductive coupling between dies may include fabricating a first inductor on a first die using a passive process, fabricating a second inductor on a second die using a semiconductor process, and assembling each die so the first and second inductor are configured as a transformer. In another embodiment, a method for matching impedance in an RF circuit fabricated using flip-chip techniques may include passing an RF input signal through a first inductor formed using a passive process, inducing a time varying magnetic flux in proximity to a second inductor formed using an active process, and passing an RF signal induced by the time varying magnetic flux through the second inductor.

Abstract translation: 提出了倒装芯片电路组件的变压器信号耦合和阻抗匹配方法。 在一个实施例中，用于在管芯之间提供电感耦合的方法可以包括使用无源工艺在第一管芯上制造第一电感器，使用半导体工艺在第二管芯上制造第二电感器，以及将每个管芯组装成第一和第二 电感器被配置为变压器。 在另一个实施例中，用于使用倒装芯片技术制造的RF电路中的阻抗匹配的方法可以包括将RF输入信号传递通过使用无源过程形成的第一电感器，从而引起接近第二电感器的时变磁通量，所述第二电感器使用 激活过程，并且将由时变磁通感应的RF信号传递通过第二电感器。

公开(公告)号：US10271745B2

公开(公告)日：2019-04-30

申请号：US15186347

申请日：2016-06-17

Applicant: QUALCOMM Incorporated

Inventor： Shiqun Gu ,  Matthew Michael Nowak ,  Kenneth Kaskoun ,  Eugene Dantsker ,  Russel Allyn Martin

IPC: A61B5/1455 ,  A61B5/024 ,  A61B5/145 ,  A61B5/00

Abstract: Examples of monolithic integrated emitter-detector array in a flexible substrate for biometric sensing and associated devices and methods are disclosed. One disclosed example device includes a flexible substrate; a first array of emitters embedded in the flexible substrate, the first array of emitters configured to emit first electromagnetic (EM) signals; a first array of detectors embedded in the flexible substrate, the first array of detectors configured to detect reflections of the first EM signals; a first scanning circuit coupled to the first array of emitters, the first scanning circuit configured to selectively activate individual emitters of the first array of emitters; and a first sensing circuit coupled to individual detectors of the first array of detectors, the first sensing circuit configured to receive a detection signal from at least one of the detectors of the first array of detectors.

公开(公告)号：US10242957B2

公开(公告)日：2019-03-26

申请号：US14633934

申请日：2015-02-27

Applicant: QUALCOMM Incorporated

Inventor： Daeik Daniel Kim ,  Changhan Hobie Yun ,  Mario Francisco Velez ,  David Francis Berdy ,  Chengjie Zuo ,  Jonghae Kim ,  Matthew Michael Nowak

IPC: H01L23/60 ,  H01L23/31 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00 ,  H01L23/552

Abstract: Ground shielding is achieved by a conductor shield having conductive surfaces that immediately surround individual chips within a multichip module or device, such as a multichip module or device with flip-chip (FC) bumps. Intra-module shielding between individual chips within the multichip module or device is achieved by electromagnetic or radio-signal (RF) isolation provided by the surfaces of the conductor shield immediately surrounding each of the chips. The conductor shield is directly connected to one or more grounded conductor portions of a substrate or interposer to ensure reliable grounding.

公开(公告)号：US10043796B2

公开(公告)日：2018-08-07

申请号：US15097142

申请日：2016-04-12

Applicant: QUALCOMM Incorporated

Inventor： Vladimir Machkaoutsan ,  Stanley Seungchul Song ,  Mustafa Badaroglu ,  John Jianhong Zhu ,  Junjing Bao ,  Jeffrey Junhao Xu ,  Da Yang ,  Matthew Michael Nowak ,  Choh Fei Yeap

IPC: H01L29/06 ,  H01L27/088 ,  H01L27/02 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/423 ,  H01L27/06

Abstract: A device includes a substrate, a first nanowire field effect transistor (FET), and a second nanowire FET positioned between the substrate and the first nanowire FET. The device also includes a first nanowire electrically coupled to the first nanowire FET and to the second nanowire FET.

公开(公告)号：US20170221884A1

公开(公告)日：2017-08-03

申请号：US15097142

申请日：2016-04-12

Applicant: QUALCOMM Incorporated

Inventor： Vladimir Machkaoutsan ,  Stanley Seungchul Song ,  Mustafa Badaroglu ,  John Jianhong Zhu ,  Junjing Bao ,  Jeffrey Junhao Xu ,  Da Yang ,  Matthew Michael Nowak ,  Choh Fei Yeap

IPC: H01L27/088 ,  H01L29/06 ,  H01L21/8234 ,  H01L27/02

CPC classification number: H01L27/088 ,  H01L21/823418 ,  H01L21/823475 ,  H01L21/823481 ,  H01L21/823487 ,  H01L21/823885 ,  H01L27/0207 ,  H01L27/0688 ,  H01L29/0649 ,  H01L29/0669 ,  H01L29/0676 ,  H01L29/42392

Abstract: A device includes a substrate, a first nanowire field effect transistor (FET), and a second nanowire FET positioned between the substrate and the first nanowire FET. The device also includes a first nanowire electrically coupled to the first nanowire FET and to the second nanowire FET.

公开(公告)号：US20170117358A1

公开(公告)日：2017-04-27

申请号：US14920851

申请日：2015-10-22

Applicant: QUALCOMM Incorporated

Inventor： Daeik Daniel Kim ,  Changhan Hobie Yun ,  Je-Hsiung Jeffrey Lan ,  Niranjan Sunil Mudakatte ,  Jonghae Kim ,  Matthew Michael Nowak

IPC: H01L29/06 ,  H01L21/78 ,  H01L21/762 ,  H01L21/768 ,  H01L23/48 ,  H01L29/78

CPC classification number: H01L29/0653 ,  H01L21/762 ,  H01L21/76224 ,  H01L21/76898 ,  H01L21/78 ,  H01L21/823481 ,  H01L23/3128 ,  H01L23/481 ,  H01L29/78

Abstract: Isolated complementary metal-oxide semiconductor (CMOS) devices for radio-frequency (RF) circuits are disclosed. In some aspects, an RF circuit includes CMOS devices, a silicon substrate having doped regions that define the CMOS devices, and a trench through the silicon substrate. The trench through the silicon substrate forms a continuous channel around the doped regions of one of the CMOS devices to electrically isolate the CMOS device from other CMOS devices embodied on the silicon substrate. By so doing, performance characteristics of the CMOS device, such as linearity and signal isolation, may be improved over those of conventional CMOS devices (e.g., bulk CMOS).

公开(公告)号：US09620463B2

公开(公告)日：2017-04-11

申请号：US14634148

申请日：2015-02-27

Applicant: QUALCOMM Incorporated

Inventor： Daeik Daniel Kim ,  David Francis Berdy ,  Mario Francisco Velez ,  Changhan Hobie Yun ,  Chengjie Zuo ,  Jonghae Kim ,  Matthew Michael Nowak

IPC: H01L23/552 ,  H01L23/60 ,  H01L25/065 ,  H01L21/56 ,  H01L23/00 ,  H01L23/538

CPC classification number: H01L23/60 ,  H01L21/568 ,  H01L23/538 ,  H01L23/5389 ,  H01L23/552 ,  H01L24/00 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L25/0655 ,  H01L2224/04105

Abstract: Ground shielding is achieved by a conductor shield having conductive surfaces that immediately surround individual chips within a fan-out wafer level package (FOWLP) module or device. Intra-module shielding between individual chips within the FOWLP module or device is achieved by electromagnetic or radio-signal (RF) isolation provided by the surfaces of the conductor shield immediately surrounding each of the chips. The conductor shield is directly connected to one or more grounded conductor portions of a FOWLP to ensure reliable grounding.

公开(公告)号：US20160293477A1

公开(公告)日：2016-10-06

申请号：US14856418

申请日：2015-09-16

Applicant: QUALCOMM Incorporated

Inventor： Daeik Daniel Kim ,  Changhan Hobie Yun ,  Je-Hsiung Jeffrey Lan ,  Mario Francisco Velez ,  Jonghae Kim ,  Matthew Michael Nowak

IPC: H01L21/762 ,  H01L23/29 ,  H01L23/31 ,  H01L27/12 ,  H01L21/84

CPC classification number: H01L21/76256 ,  H01L21/76264 ,  H01L21/84 ,  H01L23/291 ,  H01L27/1203 ,  H01L29/78603

Abstract: Silicon-on-insulator (SOI) wafers employing molded substrates to improve insulation and reduce current leakage are provided. In one aspect, a SOI wafer comprises a substrate. An insulating layer (e.g., a buried oxide (BOX) layer) is disposed above the substrate to insulate an active semiconductor layer disposed above the insulating layer, from the substrate. Transistors are formed in the active semiconductor layer. To provide for improved insulation between the active semiconductor layer and the substrate to reduce leakage and improve performance of the active semiconductor layer, the substrate is provided in the form of a molded substrate. A coating layer is also disposed between the molded substrate and the insulating layer of the SOI wafer, in case, for example, the melting temperature of a molding compound used to form the molded substrate is not low enough to prevent contamination of the active semiconductor layer into the insulating layer.

Abstract translation: 提供了使用模制基板以提高绝缘性并减少漏电的绝缘体上硅（SOI）晶片。 在一个方面，SOI晶片包括衬底。 绝缘层（例如，掩埋氧化物（BOX）层）设置在衬底之上，以使绝缘层上方的有源半导体层与衬底绝缘。 晶体管形成在有源半导体层中。 为了提供有源半导体层和衬底之间的改善的绝缘，以减少有源半导体层的泄漏和改善性能，衬底以模制衬底的形式提供。 在模制基板和SOI晶片的绝缘层之间也设置涂层，例如，用于形成模制基板的模塑料的熔化温度不足以防止有源半导体层的污染 进入绝缘层。

公开(公告)号：US09425761B2

公开(公告)日：2016-08-23

申请号：US14055707

申请日：2013-10-16

Applicant: QUALCOMM Incorporated

Inventor： Chengjie Zuo ,  Jonghae Kim ,  Changhan Hobie Yun ,  Daeik Daniel Kim ,  Mario Francisco Velez ,  Je-Hsiung Lan ,  Robert Paul Mikulka ,  Matthew Michael Nowak

IPC: H03H7/01 ,  H04B1/04

CPC classification number: H03H7/0138 ,  H03H7/0115 ,  Y10T29/417

Abstract: A filter includes a glass substrate having through substrate vias. The filter also includes capacitors supported by the glass substrate. The capacitors may have a width and/or thickness less than a printing resolution. The filter also includes a 3D inductor within the substrate. The 3D inductor includes a first set of traces on a first surface of the glass substrate coupled to the through substrate vias. The 3D inductor also includes a second set of traces on a second surface of the glass substrate coupled to opposite ends of the through substrate vias. The second surface of the glass substrate is opposite the first surface of the glass substrate. The through substrate vias and traces operate as the 3D inductor. The first set of traces and the second set of traces may also have a width and/or thickness less than the printing resolution.

Abstract translation: 滤光器包括具有通过基板通孔的玻璃基板。 滤波器还包括由玻璃基板支撑的电容器。 电容器可以具有小于打印分辨率的宽度和/或厚度。 滤波器还包括衬底内的3D电感器。 3D电感器包括耦合到贯穿衬底通孔的玻璃衬底的第一表面上的第一组迹线。 3D电感器还包括耦合到贯通衬底通孔的相对端的玻璃衬底的第二表面上的第二组迹线。 玻璃基板的第二表面与玻璃基板的第一表面相对。 贯通衬底通孔和迹线作为3D电感器工作。 第一组迹线和第二组迹线也可以具有小于打印分辨率的宽度和/或厚度。

公开(公告)号：US09343135B2

公开(公告)日：2016-05-17

申请号：US14072537

申请日：2013-11-05

Applicant: QUALCOMM Incorporated

Inventor： Xiaochun Zhu ,  Steven M. Millendorf ,  Xu Guo ,  David M. Jacobson ,  Kangho Lee ,  Seung H. Kang ,  Matthew Michael Nowak

IPC: G11C11/16 ,  G09C1/00 ,  H04L9/08 ,  H04L9/32

CPC classification number: G11C11/1695 ,  G09C1/00 ,  G11C11/161 ,  G11C11/1673 ,  G11C11/1675 ,  H04L9/0866 ,  H04L9/3278 ,  H04L2209/12

Abstract: One feature pertains to a method of implementing a physically unclonable function. The method includes initializing an array of magnetoresistive random-access memory (MRAM) cells to a first logical state, where each of the MRAM cells have a random transition voltage that is greater than a first voltage and less than a second voltage. The transition voltage represents a voltage level that causes the MRAM cells to transition from the first logical state to a second logical state. The method further includes applying a programming signal voltage to each of the MRAM cells of the array to cause at least a portion of the MRAM cells of the array to randomly change state from the first logical state to the second logical state, where the programming signal voltage is greater than the first voltage and less than the second voltage.

Abstract translation: 一个特征涉及实现物理上不可克隆功能的方法。 该方法包括将磁阻随机存取存储器（MRAM）单元的阵列初始化为第一逻辑状态，其中每个MRAM单元具有大于第一电压且小于第二电压的随机转变电压。 转换电压表示使MRAM单元从第一逻辑状态转换到第二逻辑状态的电压电平。 该方法还包括将编程信号电压施加到阵列的每个MRAM单元，以使阵列的MRAM单元的至少一部分随机地将状态从第一逻辑状态改变到第二逻辑状态，其中编程信号 电压大于第一电压且小于第二电压。