公开(公告)号：US20210159315A1

公开(公告)日：2021-05-27

申请号：US17068378

申请日：2020-10-12

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yasuhiro OKAMOTO ,  Nobuo MACHIDA

IPC: H01L29/16 ,  H01L29/66 ,  H01L29/739 ,  H01L29/08 ,  H01L29/417 ,  H01L29/423

Abstract: To improve an on-resistance of a semiconductor device. A plurality of collector regions are formed at a predetermined interval on a bottom surface of a drift layer made of SiC. Next, on the bottom surface of the drift layer, both of the drift layer and a collector region via a silicide layer are connected to a collector electrode.

公开(公告)号：US20200161445A1

公开(公告)日：2020-05-21

申请号：US16597600

申请日：2019-10-09

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Hironobu MIYAMOTO ,  Yasuhiro OKAMOTO ,  Kenichi HISADA ,  Koichi ARAI ,  Nobuo MACHIDA

IPC: H01L29/66 ,  H01L29/16 ,  H01L29/36 ,  H01L29/417

Abstract: An n-type epitaxial layer is formed on an n-type semiconductor substrate made of silicon carbide. p-type body regions are formed in the epitaxial layer, and n-type source region is formed in the body region. On the body region between the source region and the epitaxial layer, a gate electrode is formed via a gate dielectric film, and an interlayer insulating film having an opening is formed so as to cover the gate electrode. A source electrode electrically connected to the source region and the body regions is formed in the opening. A recombination layer is formed between the body region and a basal plane dislocation is a layer having point defect density higher than that of the epitaxial layer located directly under the recombination layer or having a metal added to the epitaxial layer.

公开(公告)号：US20190237577A1

公开(公告)日：2019-08-01

申请号：US16223839

申请日：2018-12-18

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yasuhiro OKAMOTO ,  Nobuo MACHIDA ,  Koichi ARAI ,  Kenichi HISADA ,  Yasunori YAMASHITA ,  Satoshi EGUCHI ,  Hironobu MIYAMOTO ,  Atsushi SAKAI ,  Katsumi EIKYU

IPC: H01L29/78 ,  H01L29/16 ,  H01L29/423 ,  H01L29/36 ,  H01L29/66 ,  H01L21/02 ,  H01L21/04 ,  H01L29/10 ,  H01L29/08

CPC classification number: H01L29/7813 ,  H01L21/02164 ,  H01L21/02271 ,  H01L21/02378 ,  H01L21/02529 ,  H01L21/02634 ,  H01L21/0274 ,  H01L21/0465 ,  H01L21/0475 ,  H01L21/049 ,  H01L29/0696 ,  H01L29/0865 ,  H01L29/0882 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/36 ,  H01L29/4236 ,  H01L29/45 ,  H01L29/4916 ,  H01L29/66068

Abstract: A drift layer is formed over a semiconductor substrate which is an SiC substrate. The drift layer includes first to third n-type semiconductor layers and a p-type impurity region. Herein, an impurity concentration of the second n-type semiconductor layer is higher than an impurity concentration of the first n-type semiconductor layer and an impurity concentration of the third n-type semiconductor layer. Also, in plan view, the second semiconductor layer located between the p-type impurity regions adjacent to each other overlaps with at least a part of a gate electrode formed in a trench.

公开(公告)号：US20190198663A1

公开(公告)日：2019-06-27

申请号：US16192480

申请日：2018-11-15

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Atsushi SAKAI ,  Katsumi EIKYU ,  Satoshi EGUCHI ,  Nobuo MACHIDA ,  Koichi ARAI ,  Yasuhiro OKAMOTO ,  Kenichi HISADA ,  Yasunori YAMASHITA

IPC: H01L29/78 ,  H01L29/16 ,  H01L29/08 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L29/7813 ,  H01L29/0865 ,  H01L29/1608 ,  H01L29/4236 ,  H01L29/66068 ,  H01L29/66734

Abstract: To improve characteristics of a semiconductor device. A first p-type semiconductor region having an impurity of a conductivity type opposite from that of a drift layer is arranged in the drift layer below a trench, and a second p-type semiconductor region is further arranged that is spaced at a distance from a region where the trench is formed as seen from above and that has the impurity of the conductivity type opposite from that of the drift layer. The second p-type semiconductor region is configured by a plurality of regions arranged at a space in a Y direction (depth direction in the drawings). Thus, it is possible to reduce the specific on-resistance while maintaining the breakdown voltage of the gate insulating film by providing the first and second p-type semiconductor regions and further by arranging the second p-type semiconductor region spaced by the space.

公开(公告)号：US20180219089A1

公开(公告)日：2018-08-02

申请号：US15841676

申请日：2017-12-14

Applicant: Renesas Electronics Corporation

Inventor： Tatsuo NAKAYAMA ,  Hironobu MIYAMOTO ,  Yasuhiro OKAMOTO

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/205 ,  H01L29/66

CPC classification number: H01L29/66431 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/207 ,  H01L29/402 ,  H01L29/42376 ,  H01L29/66462 ,  H01L29/7783 ,  H01L29/7786 ,  H01L29/7787 ,  H01L29/7789

Abstract: A mesa portion of a semiconductor device, which includes a channel base layer formed of a first nitride semiconductor layer, a channel layer formed of a second nitride semiconductor layer, a barrier layer formed of a third nitride semiconductor layer, a mesa-type fourth nitride semiconductor layer, a gate insulating film that covers the mesa portion, and a gate electrode formed over the gate insulating film, is used as a co-doped layer. The mesa portion is used as the co-doped layer, so that interface charges generated at an interface between the gate insulating film and the mesa portion can be cancelled by p-type impurity or n-type impurity in the co-doped layer and a threshold potential can be improved. Further, the fourth nitride semiconductor layer is n-type until the gate insulating film is formed, and the fourth nitride semiconductor layer is made neutral or p-type after the gate insulating film is formed.

公开(公告)号：US20180026099A1

公开(公告)日：2018-01-25

申请号：US15604848

申请日：2017-05-25

Applicant: Renesas Electronics Corporation

Inventor： Hironobu MIYAMOTO ,  Tatsuo NAKAYAMA ,  Atsushi TSUBOI ,  Yasuhiro OKAMOTO ,  Hiroshi KAWAGUCHI

IPC: H01L29/10 ,  H01L29/20 ,  H01L29/66 ,  H01L29/423 ,  H01L23/528 ,  H01L23/522 ,  H01L29/778 ,  H01L29/205

CPC classification number: H01L29/1087 ,  H01L23/5226 ,  H01L23/5286 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/41758 ,  H01L29/4236 ,  H01L29/42364 ,  H01L29/452 ,  H01L29/66462 ,  H01L29/7783 ,  H01L29/7787

Abstract: Properties of a semiconductor device are improved. A semiconductor device is configured so as to include a voltage clamp layer, a channel underlayer, a channel layer, and a barrier layer, which are formed in order above a substrate, a trench that extends up to the middle of the channel layer while penetrating through the barrier layer, a gate electrode disposed within the trench with a gate insulating film in between, a source electrode and a drain electrode formed above the barrier layer on both sides of the gate electrode, and a fourth electrode electrically coupled to the voltage clamp layer. The fourth electrode is electrically isolated from the source electrode, and a voltage applied to the fourth electrode is different from a voltage applied to the source electrode. Consequently, threshold control can be performed. For example, a threshold of a MISFET can be increased.

公开(公告)号：US20170162683A1

公开(公告)日：2017-06-08

申请号：US15437559

申请日：2017-02-21

Applicant: Renesas Electronics Corporation

Inventor： Tatsuo NAKAYAMA ,  Hironobu MIYAMOTO ,  Yasuhiro OKAMOTO ,  Yoshinao MIURA ,  Takashi INOUE

IPC: H01L29/778 ,  H01L29/15 ,  H01L29/423 ,  H01L29/40 ,  H01L23/535 ,  H01L29/66 ,  H01L21/3065 ,  H01L21/027 ,  H01L29/205 ,  H01L29/06

CPC classification number: H01L29/7787 ,  H01L21/0274 ,  H01L21/3065 ,  H01L23/535 ,  H01L29/0649 ,  H01L29/1066 ,  H01L29/1075 ,  H01L29/1087 ,  H01L29/155 ,  H01L29/2003 ,  H01L29/201 ,  H01L29/205 ,  H01L29/402 ,  H01L29/4175 ,  H01L29/41758 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/66462 ,  H01L29/7783 ,  H01L29/7786

Abstract: A semiconductor device includes a first nitride semiconductor layer formed over a substrate, a second nitride semiconductor layer formed over the first nitride semiconductor layer, a third nitride semiconductor layer formed over the second nitride semiconductor layer, a fourth nitride semiconductor layer formed over the third nitride semiconductor layer, a trench that penetrates the fourth nitride semiconductor layer and reaches as far as the third nitride semiconductor layer, a gate electrode disposed by way of a gate insulation film in the trench, a first electrode and a second electrode formed respectively over the fourth nitride semiconductor layer on both sides of the gate electrode, and a coupling portion for coupling the first electrode and the first nitride semiconductor layer.

公开(公告)号：US20160240648A1

公开(公告)日：2016-08-18

申请号：US15142601

申请日：2016-04-29

Applicant: Renesas Electronics Corporation

Inventor： Yasuhiro OKAMOTO ,  Tatsuo NAKAYAMA ,  Takashi INOUE

IPC: H01L29/778 ,  H01L29/66 ,  H01L29/423 ,  H01L21/28 ,  H01L29/20 ,  H01L29/205

CPC classification number: H01L29/7787 ,  H01L21/28264 ,  H01L29/0692 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/4236 ,  H01L29/42364 ,  H01L29/42368 ,  H01L29/66462 ,  H01L29/7786 ,  H01L29/7789

Abstract: A semiconductor device includes a first nitride semiconductor layer formed above a substrate, a second nitride semiconductor layer formed over the first nitride semiconductor layer and having a band gap larger than that of the first nitride semiconductor layer, a trench passing through the second nitride semiconductor layer and into the first nitride semiconductor layer, a gate insulation film formed in the trench, and a gate electrode disposed by way of the gate insulation film in an inside of the trench. The corner of the trench between a side wall of the trench and a bottom of the trench includes a rounded shape, and a corner of the gate insulation film in contact with the corner of the trench includes a rounded shape.

Abstract translation: 半导体器件包括形成在衬底上的第一氮化物半导体层，形成在第一氮化物半导体层上并且具有比第一氮化物半导体层的带隙大的带隙的第二氮化物半导体层，穿过第二氮化物半导体层 并且形成在沟槽中的第一氮化物半导体层，栅极绝缘膜以及沟槽内部通过栅极绝缘膜设置的栅电极。 沟槽的侧壁和沟槽的底部之间的沟槽的角部包括圆形形状，并且与沟槽的角部接触的栅极绝缘膜的角部包括圆形。