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    THRESHOLD-MONITORING, CONDITIONAL-RESET IMAGE SENSOR
    31.
    发明申请
    THRESHOLD-MONITORING, CONDITIONAL-RESET IMAGE SENSOR 审中-公开
    阈值监控，条件复位图像传感器

    公开(公告)号：US20160028985A1

    公开(公告)日：2016-01-28

    申请号：US14772311

    申请日：2014-03-14

    Applicant: RAMBUS INC.

    Inventor： Thomas Vogelsang ,  Michael Guidash ,  Song Xue ,  Maxim Smirnov ,  Craig M. Smith ,  Jay Endsley ,  James E. Harris

    IPC: H04N5/3745 ,  H04N5/376

    CPC classification number: H04N5/3745 ,  H01L27/14634 ,  H01L27/14641 ,  H04N5/347 ,  H04N5/376

    Abstract: An image sensor architecture with multi-bit sampling is implemented within an image sensor system. A pixel signal produced in response to light incident upon a photosensitive element is converted to a multiple-bit digital value representative of the pixel signal. If the pixel signal exceeds a sampling threshold, the photosensitive element is reset. During an image capture period, digital values associated with pixel signals that exceed a sampling threshold are accumulated into image data.

    Abstract translation: 在图像传感器系统中实现具有多位采样的图像传感器架构。 响应于入射到感光元件上的光而产生的像素信号被转换成表示像素信号的多位数字值。 如果像素信号超过采样阈值，则光敏元件被复位。 在图像捕获期间，与超过采样阈值的像素信号相关联的数字值被累积到图像数据中。

    Memory systems and methods for improved power management
    33.
    发明授权
    Memory systems and methods for improved power management 有权

    公开(公告)号：US11710520B2

    公开(公告)日：2023-07-25

    申请号：US17702475

    申请日：2022-03-23

    Applicant: Rambus Inc.

    Inventor： Frederick A. Ware ,  James E. Harris

    IPC: G11C8/12 ,  G11C11/4093 ,  G11C5/04 ,  G11C5/06 ,  G11C7/22

    CPC classification number: G11C11/4093 ,  G11C5/04 ,  G11C5/063 ,  G11C7/22 ,  G11C8/12

    Abstract: A memory module with multiple memory devices includes a buffer system that manages communication between a memory controller and the memory devices. Each memory device supports an access mode and a low-power mode, the latter used to save power for devices that are not immediately needed. The module provides granular power management using a chip-select decoder that decodes chip-select signals from the memory controller into power-state signals that determine which of the memory devices are in which of the modes. Devices can thus be brought out of the low-power mode in relatively small numbers, as needed, to limit power consumption.

    Memory Systems and Methods for Improved Power Management
    34.
    发明申请
    Memory Systems and Methods for Improved Power Management 有权

    公开(公告)号：US20220284947A1

    公开(公告)日：2022-09-08

    申请号：US17702475

    申请日：2022-03-23

    Applicant: Rambus Inc.

    Inventor： Frederick A. Ware ,  James E. Harris

    IPC: G11C11/4093 ,  G11C5/04 ,  G11C5/06 ,  G11C8/12 ,  G11C7/22

    Abstract: A memory module with multiple memory devices includes a buffer system that manages communication between a memory controller and the memory devices. Each memory device supports an access mode and a low-power mode, the latter used to save power for devices that are not immediately needed. The module provides granular power management using a chip-select decoder that decodes chip-select signals from the memory controller into power-state signals that determine which of the memory devices are in which of the modes. Devices can thus be brought out of the low-power mode in relatively small numbers, as needed, to limit power consumption.

    Memory Systems and Methods for Improved Power Management
    39.
    发明申请
    Memory Systems and Methods for Improved Power Management 审中-公开

    公开(公告)号：US20190115065A1

    公开(公告)日：2019-04-18

    申请号：US16101480

    申请日：2018-08-12

    Applicant: Rambus Inc.

    Inventor： Frederick A. Ware ,  James E. Harris

    IPC: G11C11/4093 ,  G11C7/22 ,  G11C5/04 ,  G11C5/06 ,  G11C8/12

    Abstract: A memory module with multiple memory devices includes a buffer system that manages communication between a memory controller and the memory devices. Each memory device supports an access mode and a low-power mode, the latter used to save power for devices that are not immediately needed. The module provides granular power management using a chip-select decoder that decodes chip-select signals from the memory controller into power-state signals that determine which of the memory devices are in which of the modes. Devices can thus be brought out of the low-power mode in relatively small numbers, as needed, to limit power consumption.

    HIGH DYNAMIC-RANGE IMAGE SENSOR
    40.
    发明申请
    HIGH DYNAMIC-RANGE IMAGE SENSOR 审中-公开

    公开(公告)号：US20190082125A1

    公开(公告)日：2019-03-14

    申请号：US16140862

    申请日：2018-09-25

    Applicant: Rambus Inc.

    Inventor： Craig M. Smith ,  Frank Armstrong ,  Jay Endsley ,  Thomas Vogelsang ,  James E. Harris ,  John Ladd ,  Michael Guidash

    IPC: H04N5/355 ,  H04N5/232 ,  H04N5/235 ,  H04N5/347 ,  H04N5/3745 ,  H04N9/04 ,  H04N5/361

    Abstract: A pixel array within an integrated-circuit image sensor is exposed to light representative of a scene during a first frame interval and then oversampled a first number of times within the first frame interval to generate a corresponding first number of frames of image data from which a first output image may be constructed. One or more of the first number of frames of image data are evaluated to determine whether a range of luminances in the scene warrants adjustment of an oversampling factor from the first number to a second number, if so, the oversampling factor is adjusted such that the pixel array is oversampled the second number of times within a second frame interval to generate a corresponding second number of frames of image data from which a second output image may be constructed.

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