公开(公告)号：US20220245073A1

公开(公告)日：2022-08-04

申请号：US17677714

申请日：2022-02-22

Applicant: Rambus Inc.

Inventor： Thomas J. Giovannini ,  John Eric Linstadt ,  Catherine Chen

IPC: G06F13/16 ,  G06F13/42 ,  G06F13/40

Abstract: A memory system supports single- and dual-memory-module configurations, both supporting point-to-point communication between a host (e.g., a memory controller) and the memory module or modules. Each memory module includes an address-buffer component, data-buffer components, and two sets of memory dies, each set termed a “timing rank,” that can be accessed independently. The one memory module is configured in a wide mode for the single-memory-module configuration, in which case both timing ranks work together, as a “package rank,” to communicate full-width data. Each of two memory modules are configured in a narrow mode for the dual-memory-module configuration, in which case one timing rank from each memory module communicates data in parallel to appear to the host as single package ranks. The data-buffer components support separate and configurable write and read delays for the different timing ranks on each module to provide read and write leveling within and between memory modules.

公开(公告)号：US20210279191A1

公开(公告)日：2021-09-09

申请号：US17191469

申请日：2021-03-03

Applicant: Rambus Inc.

Inventor： Ian Shaeffer ,  Thomas J. Giovannini

IPC: G06F13/16 ,  G06F12/00 ,  G11C7/10 ,  G11C7/22

Abstract: Apparatus and methods for operation of a memory controller, memory device and system are described. During operation, the memory controller transmits a read command which specifies that a memory device output data accessed from a memory core. This read command contains information which specifies whether the memory device is to commence outputting of a timing reference signal prior to commencing outputting of the data. The memory controller receives the timing reference signal if the information specified that the memory device output the timing reference signal. The memory controller subsequently samples the data output from the memory device based on information provided by the timing reference signal output from the memory device.

公开(公告)号：US20190340143A1

公开(公告)日：2019-11-07

申请号：US16405421

申请日：2019-05-07

Applicant: Rambus Inc.

Inventor： Ian Shaeffer ,  Thomas J. Giovannini

IPC: G06F13/16 ,  G11C7/10 ,  G11C7/22 ,  G06F12/00

Abstract: Apparatus and methods for operation of a memory controller, memory device and system are described. During operation, the memory controller transmits a read command which specifies that a memory device output data accessed from a memory core. This read command contains information which specifies whether the memory device is to commence outputting of a timing reference signal prior to commencing outputting of the data. The memory controller receives the timing reference signal if the information specified that the memory device output the timing reference signal. The memory controller subsequently samples the data output from the memory device based on information provided by the timing reference signal output from the memory device.

公开(公告)号：US20160293239A1

公开(公告)日：2016-10-06

申请号：US15090399

申请日：2016-04-04

Applicant: Rambus Inc.

Inventor： Thomas J. Giovannini ,  Catherine Chen ,  Scott C. Best ,  John Eric Linstadt ,  Frederick A. Ware

IPC: G11C8/08 ,  G11C29/44 ,  G06F11/07 ,  G11C8/06

CPC classification number: G06F11/079 ,  G06F11/073 ,  G06F11/0772 ,  G11C5/04 ,  G11C7/20 ,  G11C8/12 ,  G11C29/26 ,  G11C29/44

Abstract: During system initialization, each data buffer device and/or memory device on a memory module is configured with a unique (at least to the module) device identification number. In order to access a single device (rather than multiple buffers and/or memory devices), a target identification number is written to all of the devices using a command bus connected to all of the data buffer devices or memory devices, respectively. The devices whose respective device identification numbers do not match the target identification number are configured to ignore future command bus transactions (at least until the debug mode is turned off.) The selected device that is configured with a device identification number matching the target identification number is configured to respond to command bus transactions.

Abstract translation: 在系统初始化期间，存储器模块上的每个数据缓冲设备和/或存储器设备被配置为唯一（至少对于模块）设备标识号。 为了访问单个设备（而不是多个缓冲器和/或存储设备），使用分别连接到所有数据缓冲设备或存储设备的命令总线将目标识别号码写入所有设备。 各个设备标识号与目标识别号码不一致的设备被配置为忽略未来的命令总线事务（至少直到调试模式被关闭）。所选择的设备被配置有与目标识别号码相匹配的设备标识号 被配置为响应命令总线事务。

公开(公告)号：US09298228B1

公开(公告)日：2016-03-29

申请号：US14810410

申请日：2015-07-27

Applicant: Rambus Inc.

Inventor： Abhijit M. Abhyankar ,  Ravindranath Kollipara ,  Thomas J. Giovannini ,  Ming Li ,  David A. Secker ,  Arun Vaidyanath ,  Donald R. Mullen ,  Adrian F. Torres

IPC: H05K1/11 ,  H05K1/14 ,  G06F1/18

CPC classification number: G06F1/185

Abstract: A computing system having a memory riser sub-system. The computing system includes a motherboard with a memory module connector and a riser card inserted into the first memory module connector. A first mezzanine card is connected to the riser card. The first mezzanine card includes a first mezzanine memory module connector for a first memory module and a second mezzanine memory module connector for a second memory module. A memory channel electrically connects the memory controller to the first mezzanine memory module connector and the second mezzanine module connector via the motherboard, the first riser card and the first mezzanine card. The memory channel may be divided into a first data sub-channel connected to the first mezzanine memory module connector and a second data sub-channel connected to the second mezzanine memory module connector.

Abstract translation: 具有存储器提升子子系统的计算系统。 计算系统包括具有存储器模块连接器的主板和插入到第一存储器模块连接器中的转接卡。 第一个夹层卡连接到转接卡。 第一夹层卡包括用于第一存储器模块的第一夹层存储器模块连接器和用于第二存储器模块的第二夹层存储器模块连接器。 存储通道经由主板，第一转接卡和第一夹层卡将存储器控制器电连接到第一夹层存储器模块连接器和第二夹层模块连接器。 存储器通道可以被分成连接到第一夹层存储器模块连接器的第一数据子通道和连接到第二夹层存储器模块连接器的第二数据子通道。

公开(公告)号：US09165638B2

公开(公告)日：2015-10-20

申请号：US14702582

申请日：2015-05-01

Applicant: Rambus Inc.

Inventor： Thomas J. Giovannini ,  Alok Gupta ,  Ian Shaeffer ,  Steven C. Woo

IPC: G06F12/00 ,  G11C11/4076 ,  G06F3/06 ,  G06F5/06 ,  G06F1/08 ,  G11C7/10 ,  G06F13/16 ,  G06F12/06 ,  G11C11/409

CPC classification number: G11C11/4076 ,  G06F1/08 ,  G06F3/0629 ,  G06F3/0634 ,  G06F5/06 ,  G06F12/0646 ,  G06F13/1689 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/1093 ,  G11C11/409 ,  G11C11/4096 ,  G11C2207/2254

Abstract: A system that calibrates timing relationships between signals involved in performing write operations is described. This system includes a memory controller which is coupled to a set of memory chips, wherein each memory chip includes a phase detector configured to calibrate a phase relationship between a data-strobe signal and a clock signal received at the memory chip from the memory controller during a write operation. Furthermore, the memory controller is configured to perform one or more write-read-validate operations to calibrate a clock-cycle relationship between the data-strobe signal and the clock signal, wherein the write-read-validate operations involve varying a delay on the data-strobe signal relative to the clock signal by a multiple of a clock period.

公开(公告)号：US20250111873A1

公开(公告)日：2025-04-03

申请号：US18920405

申请日：2024-10-18

Applicant: Rambus Inc.

Inventor： Thomas J. Giovannini ,  Alok Gupta ,  Ian Shaeffer ,  Steven C. Woo

IPC: G11C11/4076 ,  G06F1/08 ,  G06F3/06 ,  G06F5/06 ,  G06F12/06 ,  G06F13/16 ,  G11C7/10 ,  G11C11/409 ,  G11C11/4096 ,  G11C29/02

Abstract: A system that calibrates timing relationships between signals involved in performing write operations is described. This system includes a memory controller which is coupled to a set of memory chips, wherein each memory chip includes a phase detector configured to calibrate a phase relationship between a data-strobe signal and a clock signal received at the memory chip from the memory controller during a write operation. Furthermore, the memory controller is configured to perform one or more write-read-validate operations to calibrate a clock-cycle relationship between the data-strobe signal and the clock signal, wherein the write-read-validate operations involve varying a delay on the data-strobe signal relative to the clock signal by a multiple of a clock period.

公开(公告)号：US20240428835A1

公开(公告)日：2024-12-26

申请号：US18767988

申请日：2024-07-10

Applicant: Rambus Inc.

Inventor： Andrew M. Fuller ,  Robert E. Palmer ,  Thomas J. Giovannini ,  Michael D. Bucher ,  Thoai Thai Le

IPC: G11C7/22 ,  G11C7/10

Abstract: A first-in-first-out (FIFO) storage structure within an integrated-circuit component is loaded with qualification values corresponding to respective pairs of edges expected within a timing strobe signal transmitted to the integrated-circuit component. The qualification values are sequentially output from the FIFO storage structure during respective cycles of the timing strobe signal and a gate signal is either asserted or deasserted during the respective cycles of the timing strobe signal according to the qualification values output from the FIFO storage structure.

公开(公告)号：US20240160588A1

公开(公告)日：2024-05-16

申请号：US18483043

申请日：2023-10-09

Applicant: Rambus Inc.

Inventor： Ian Shaeffer ,  Thomas J. Giovannini

IPC: G06F13/16 ,  G06F12/00 ,  G11C7/10 ,  G11C7/22

CPC classification number: G06F13/1689 ,  G06F12/00 ,  G11C7/10 ,  G11C7/1066 ,  G11C7/1093 ,  G11C7/222 ,  G11C2207/2254

Abstract: Apparatus and methods for operation of a memory controller, memory device and system are described. During operation, the memory controller transmits a read command which specifies that a memory device output data accessed from a memory core. This read command contains information which specifies whether the memory device is to commence outputting of a timing reference signal prior to commencing outputting of the data. The memory controller receives the timing reference signal if the information specified that the memory device output the timing reference signal. The memory controller subsequently samples the data output from the memory device based on information provided by the timing reference signal output from the memory device.

公开(公告)号：US11809345B2

公开(公告)日：2023-11-07

申请号：US17677714

申请日：2022-02-22

Applicant: Rambus Inc.

Inventor： Thomas J. Giovannini ,  John Eric Linstadt ,  Catherine Chen

IPC: G06F13/16 ,  G06F13/42 ,  G06F13/40

CPC classification number: G06F13/1689 ,  G06F13/1673 ,  G06F13/1678 ,  G06F13/4022 ,  G06F13/4265

Abstract: A memory system supports single- and dual-memory-module configurations, both supporting point-to-point communication between a host (e.g., a memory controller) and the memory module or modules. Each memory module includes an address-buffer component, data-buffer components, and two sets of memory dies, each set termed a “timing rank,” that can be accessed independently. The one memory module is configured in a wide mode for the single-memory-module configuration, in which case both timing ranks work together, as a “package rank,” to communicate full-width data. Each of two memory modules are configured in a narrow mode for the dual-memory-module configuration, in which case one timing rank from each memory module communicates data in parallel to appear to the host as single package ranks. The data-buffer components support separate and configurable write and read delays for the different timing ranks on each module to provide read and write leveling within and between memory modules.