公开(公告)号：US20110260233A1

公开(公告)日：2011-10-27

申请号：US12886421

申请日：2010-09-20

申请人： Bich-Yen Nguyen ,  Carlos Mazure ,  Richard Ferrant

发明人： Bich-Yen Nguyen ,  Carlos Mazure ,  Richard Ferrant

IPC分类号： H01L29/788 ,  H01L21/336 ,  H01L29/78

CPC分类号： H01L21/823462 ,  H01L21/823481 ,  H01L21/84 ,  H01L27/0705 ,  H01L27/1203 ,  H01L27/1207 ,  H01L29/7881

摘要： The present invention relates to a semiconductor device that has a semiconductor-on-insulator (SeOI) structure, which includes a substrate, an insulating layer such as an oxide layer on the substrate and a semiconductor layer on the insulating layer with a field-effect-transistor (FET) formed in the SeOI structure from the substrate and deposited layers, wherein the FET has a channel region in the substrate, a gate dielectric layer that is made from at least a part of the oxide layer of the SeOI structure; and a gate electrode that is formed at least partially from a part of the semiconductor layer of the SeOI structure. The invention further relates to a method of forming one or more field-effect-transistors or metal-oxide-semiconductor transistors from a semiconductor-on-insulator structure that involves patterning and etching the SeOI structure, forming shallow trench isolations, depositing insulating, metal or semiconductor layers, and removing mask and/or pattern layers.

摘要翻译： 本发明涉及一种具有绝缘体上半导体（SeOI）结构的半导体器件，其包括衬底，绝缘层如衬底上的氧化物层和具有场效应的绝缘层上的半导体层 - 晶体管（FET），其从所述衬底和沉积层形成在所述SeOI结构中，其中所述FET在所述衬底中具有沟道区;栅极介电层，其由所述SeOI结构的所述氧化物层的至少一部分制成; 以及至少部分地由SeOI结构的半导体层的一部分形成的栅电极。 本发明还涉及从绝缘体上半导体结构形成一个或多个场效应晶体管或金属氧化物半导体晶体管的方法，该方法包括图案化和蚀刻SeOI结构，形成浅沟槽隔离，沉积绝缘金属 或半导体层，以及去除掩模和/或图案层。

公开(公告)号：US20110233675A1

公开(公告)日：2011-09-29

申请号：US13039167

申请日：2011-03-02

申请人： Carlos Mazure ,  Richard Ferrant ,  Bich-Yen Nguyen

发明人： Carlos Mazure ,  Richard Ferrant ,  Bich-Yen Nguyen

IPC分类号： H01L27/092 ,  H01L21/28

CPC分类号： H01L27/1104 ,  G11C11/412 ,  H01L21/84 ,  H01L27/1203

摘要： An SRAM-type memory cell that includes a semiconductor on insulator substrate having a thin film of semiconductor material separated from a base substrate by an insulating layer; and six transistors such as two access transistors, two conduction transistors and two charge transistors arranged so as to form with the conduction transistors two back-coupled inverters. Each of the transistors has a back control gate formed in the base substrate below the channel and able to be biased in order to modulate the threshold voltage of the transistor, with a first back gate line connecting the back control gates of the access transistors to a first potential and a second back gate line connecting the back control gates of the conduction transistors and charge transistors to a second potential. The first and second potentials can be modulated according to the type of cell control operation.

摘要翻译： 一种SRAM型存储单元，包括绝缘体上半导体衬底，其具有通过绝缘层从基底衬底分离的半导体材料薄膜; 以及六个晶体管，例如两个存取晶体管，两个导通晶体管和两个电荷晶体管，其布置成与导通晶体管形成两个反向耦合的反相器。 每个晶体管具有形成在通道下方的基底衬底中的后控制栅极，并且能够被偏置以便调制晶体管的阈值电压，第一背栅极线将存取晶体管的背控制栅极连接到 第一电位和第二背栅极线，其将导通晶体管和电荷晶体管的背控制栅极连接到第二电位。 第一和第二电位可以根据电池控制操作的类型进行调制。

公开(公告)号：US20110134698A1

公开(公告)日：2011-06-09

申请号：US12946135

申请日：2010-11-15

申请人： Carlos Mazure ,  Richard Ferrant

发明人： Carlos Mazure ,  Richard Ferrant

IPC分类号： G11C16/04 ,  H01L29/772 ,  H01L21/336

CPC分类号： H01L29/7881 ,  H01L21/28273 ,  H01L27/11521 ,  H01L29/42328 ,  H01L29/42336

摘要： The invention relates to a flash memory cell having a FET transistor with a floating gate on a semiconductor-on-insulator (SOI) substrate composed of a thin film of semiconductor material separated from a base substrate by an insulating buried oxide (BOX) layer, The transistor has in the thin film, a channel, with two control gates, a front control gate located above the floating gate and separated from it by an inter-gate dielectric, and a back control gate located within the base substrate directly under the insulating (BOX) layer and separated from the channel by only the insulating (BOX) layer. The two control gates are designed to be used in combination to perform a cell programming operation. The invention also relates to a memory array made up of a plurality of memory cells according to the first aspect of the invention, which can be in an array of rows and columns, and a method of fabricating such memory cells and memory arrays.

摘要翻译： 本发明涉及一种闪存单元，其具有在绝缘体上绝缘体（SOI）衬底上具有浮置栅极的FET晶体管，该半导体材料由通过绝缘掩埋氧化物（BOX）层从基底衬底分离的半导体材料薄膜构成， 晶体管在薄膜中具有通道，具有两个控制栅极，位于浮置栅极上方的前控制栅极，并通过栅极间电介质与栅极间绝缘体分离，以及位于绝缘子下方的基底衬底内的反控制栅极 （BOX）层，并且仅通过绝缘（BOX）层与沟道分离。 两个控制门被设计成组合使用以执行单元编程操作。 本发明还涉及由根据本发明的第一方面的多个存储单元组成的存储器阵列，其可以是行和列的阵列，以及制造这种存储单元和存储器阵列的方法。

公开(公告)号：US20110134690A1

公开(公告)日：2011-06-09

申请号：US12898230

申请日：2010-10-05

申请人： Carlos Mazure ,  Richard Ferrant

发明人： Carlos Mazure ,  Richard Ferrant

IPC分类号： G11C11/34 ,  H01L29/772 ,  H01L21/336

CPC分类号： G11C11/404 ,  G11C2211/4016 ,  H01L27/10802 ,  H01L27/1203 ,  H01L29/42356 ,  H01L29/7841

摘要： The invention relates to a method of controlling a DRAM memory cell of an FET transistor on a semiconductor-on-insulator substrate that includes a thin film of semiconductor material separated from a base substrate by an insulating layer or BOX layer, the transistor having a channel and two control gates, a front control gate being arranged on top of the channel and separated from the latter by a gate dielectric and a back control gate being arranged in the base substrate and separated from the channel by the insulating layer (BOX). In a cell programming operation, the front control gate and the back control gate are operated jointly by applying a first voltage to the front control gate and a second voltage to the back control gate, with the first voltage being lower in amplitude than the voltage needed to program the cell when no voltage is applied to the back control gate.

摘要翻译： 本发明涉及一种控制绝缘体上半导体衬底上的FET晶体管的DRAM存储单元的方法，该方法包括通过绝缘层或BOX层从基底衬底分离的半导体材料的薄膜，晶体管具有通道 和两个控制栅极，前控制栅极布置在通道的顶部并且由栅介质和背控制栅极分隔开，栅极电介质和背控制栅极被布置在基底衬底中并且通过绝缘层（BOX）与通道分离。 在单元编程操作中，前控制栅极和后控制栅极通过向前控制栅极施加第一电压和向后控制栅极施加第二电压来共同操作，第一电压的幅度低于所需的电压 当没有电压施加到后控制门时对单元进行编程。

公开(公告)号：US08310866B2

公开(公告)日：2012-11-13

申请号：US12168671

申请日：2008-07-07

申请人： Rainer Leuschner ,  Ulrich Klostermann ,  Richard Ferrant

发明人： Rainer Leuschner ,  Ulrich Klostermann ,  Richard Ferrant

IPC分类号： G11C11/02 ,  G11C7/00 ,  H01L21/00

CPC分类号： G11C7/04 ,  B82Y25/00 ,  B82Y40/00 ,  G11C11/16 ,  G11C11/1675 ,  H01F10/3254 ,  H01F10/3272 ,  H01F41/307 ,  H01L27/228 ,  H01L43/08 ,  H01L43/12

摘要： A thermally-assisted MRAM structure which is programmable at a writing mode operating temperature is presented and includes an anti-ferromagnet, an artificial anti-ferromagnet, a barrier layer, and a free magnetic layer. The anti-ferromagnet is composed of a material having a blocking temperature Tb which is lower than the writing mode operating temperature of the magnetic random access memory structure. The artificial anti-ferromagnet is magnetically coupled to the anti-ferromagnet, and includes first and second magnetic layers, and a coupling layer interposed therebetween, the first and second magnetic layers having different Curie point temperatures. The barrier layer is positioned to be between the second magnetic layer and the free magnetic layer.

摘要翻译： 提出了一种在写入模式工作温度下可编程的热辅助MRAM结构，其包括反铁磁体，人造抗铁磁体，阻挡层和自由磁性层。 抗铁磁体由具有比磁性随机存取存储器结构的写入模式工作温度低的阻挡温度Tb的材料构成。 人造抗铁磁体磁耦合到抗铁磁体，并且包括第一和第二磁性层以及插入其间的耦合层，第一和第二磁性层具有不同的居里点温度。 阻挡层被定位在第二磁性层和自由磁性层之间。

公开(公告)号：US07994560B2

公开(公告)日：2011-08-09

申请号：US12173702

申请日：2008-07-15

申请人： Christian Caillat ,  Richard Ferrant

发明人： Christian Caillat ,  Richard Ferrant

IPC分类号： H01L29/94

CPC分类号： H01L27/10823 ,  H01L27/0218 ,  H01L27/10829 ,  H01L27/10876 ,  H01L27/10885 ,  H01L27/1203

摘要： An integrated circuit includes a substrate and at least one active region. A transistor produced in the active region separated from the substrate. This transistor includes a source or drain first region and a drain or source second region which are connected by a channel. A gate structure is position on top of said channel and operates to control the channel. The gate structure is formed in a trench whose sidewalls have a shape which converges (narrows) in the width dimension towards the substrate. A capacitor is also formed having a first electrode, a second electrode and a dielectric layer between the electrodes. This capacitor is also formed in a trench. An electrode line is connected to the first electrode of the capacitor. The second electrode of the capacitor is formed in a layer shared in common with at least part of the drain or source second region of the transistor. A bit line is located beneath the gate structure. The integrated circuit may, for example, be a DRAM memory cell.

摘要翻译： 集成电路包括衬底和至少一个有源区。 在与基板分离的有源区中产生的晶体管。 该晶体管包括源极或漏极第一区域以及通过沟道连接的漏极或源极第二区域。 栅极结构位于所述通道的顶部并且用于控制通道。 栅极结构形成在其侧壁具有朝向衬底的宽度尺寸收敛（窄））的形状的沟槽中。 电容器也形成为具有在电极之间的第一电极，第二电极和电介质层。 该电容器也形成在沟槽中。 电极线连接到电容器的第一电极。 电容器的第二电极形成在与晶体管的漏极或源极第二区域的至少一部分共同共享的层中。 位线位于门结构下方。 集成电路例如可以是DRAM存储单元。

公开(公告)号：US06995997B2

公开(公告)日：2006-02-07

申请号：US10862057

申请日：2004-06-04

申请人： Richard Ferrant

发明人： Richard Ferrant

IPC分类号： G11C15/00

CPC分类号： G11C15/04

摘要： A CAM cell with masking made in the form of an integrated circuit, including a first storage cell including a first transistor, first and second inverters in anti-parallel, and a second transistor; a comparison cell, including third and fourth transistors controlling a fifth transistor, connected in series with a sixth inhibiting transistor to a result line; and a second storage cell, including a seventh transistor in series with two inverters in anti-parallel and an eighth transistor, the second storage cell controlling the inhibiting transistor. The first, second, seventh, and eighth transistors may be N-channel transistors, and the third, fourth, fifth, and sixth transistors may be P-channel transistors.

摘要翻译： 具有以集成电路形式形成的掩蔽的CAM单元，包括：第一存储单元，包括第一晶体管，反并联的第一和第二反相器以及第二晶体管; 比较单元，包括控制第五晶体管的第三和第四晶体管，与第六抑制晶体管串联连接到结果行; 以及第二存储单元，其包括与反并联的两个反相器串联的第七晶体管和第八晶体管，所述第二存储单元控制所述抑制晶体管。 第一，第二，第七和第八晶体管可以是N沟道晶体管，并且第三，第四，第五和第六晶体管可以是P沟道晶体管。

公开(公告)号：US20050174873A1

公开(公告)日：2005-08-11

申请号：US11096970

申请日：2005-04-01

申请人： Richard Ferrant ,  Serguei Okhonin ,  Eric Carman ,  Michel Bron

发明人： Richard Ferrant ,  Serguei Okhonin ,  Eric Carman ,  Michel Bron

IPC分类号： G11C20060101 ,  G11C8/00 ,  G11C11/00 ,  G11C11/404 ,  G11C11/406 ,  G11C11/4097

CPC分类号： G11C11/404 ,  G11C7/18 ,  G11C8/08 ,  G11C11/406 ,  G11C11/40618 ,  G11C11/4097 ,  G11C2211/4016 ,  G11C2211/4065 ,  H01L21/84 ,  H01L27/10802 ,  H01L27/10844 ,  H01L27/1203 ,  H01L29/7841

摘要： There are many inventions described and illustrated herein. In a first aspect, the present invention is directed to a memory device and technique of reading data from and writing data into memory cells of the memory device. In this regard, in one embodiment of this aspect of the invention, the memory device and technique for operating that device that minimizes, reduces and/or eliminates the debilitating affects of the charge pumping phenomenon. This embodiment of the present invention employs control signals that minimize, reduce and/or eliminate transitions of the amplitudes and/or polarities. In another embodiment, the present invention is a semiconductor memory device including a memory array comprising a plurality of semiconductor dynamic random access memory cells arranged in a matrix of rows and columns. Each semiconductor dynamic random access memory cell includes a transistor having a source region, a drain region, a electrically floating body region disposed between and adjacent to the source region and the drain region, and a gate spaced apart from, and capacitively coupled to, the body region. Each transistor includes a first state representative of a first charge in the body region, and a second data state representative of a second charge in the body region. Further, each row of semiconductor dynamic random access memory cells includes an associated source line which is connected to only the semiconductor dynamic random access memory cells of the associated row.

公开(公告)号：US20050157534A1

公开(公告)日：2005-07-21

申请号：US10627955

申请日：2003-07-25

申请人： Richard Ferrant ,  Francois Jacquet

发明人： Richard Ferrant ,  Francois Jacquet

IPC分类号： G11C11/406 ,  G11C11/24

CPC分类号： G11C11/406

摘要： A DRAM including an array of storage elements arranged in lines and columns, and for each column: write means adapted to biasing at least a selected one of the elements to a charge level chosen from among a first predetermined high level and a second predetermined low level, combined with read circuitry adapted to determining whether the stored charge level is greater or smaller than a predetermined charge level; and isolation circuitry adapted to isolating the array from the read and/or write means, each column further including refreshment means, distinct from the read and write circuit, for increasing, beyond the first and second predetermined levels, the charge stored in a storage element.

摘要翻译： 一种DRAM，包括排列成行和列的存储元件的阵列，并且用于每列：写入装置，其适于将至少一个所选元素偏置到从第一预定高电平和第二预定低电平中选择的电荷电平 与读取电路组合，适于确定所存储的电荷电平是否大于或小于预定电荷电平; 以及隔离电路，其适于将阵列与读取和/或写入装置隔离，每列还包括与读取和写入电路不同的刷新装置，用于在第一和第二预定级别之外增加存储在存储元件中的电荷 。

公开(公告)号：US06920075B2

公开(公告)日：2005-07-19

申请号：US10450803

申请日：2001-12-14

申请人： Richard Ferrant

发明人： Richard Ferrant

IPC分类号： G11C7/06 ,  G11C7/10 ,  G11C11/4091 ,  G11C7/00

CPC分类号： G11C11/4091 ,  G11C7/062 ,  G11C7/1006

摘要： The invention concerns an amplifier (1), capable of being controlled by an activation signal, for reading storage cells of a crossbar network comprising, for each column, a direct bit line (BLdi) and a reference bit line (BLri), the amplifier being common to two columns and producing an OR-Exclusive type combination of the states of the cells read in said two columns.

摘要翻译： 本发明涉及一种能够被激活信号控制的放大器（1），用于读取交叉开关网络的存储单元，其包括针对每列的直接位线（BLdi）和参考位线（BLri），放大器 对于两列是共同的，并且产生在所述两列中读取的单元的状态的OR-Exclusive类型组合。