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47 条记录 (耗时 0.032 秒)

    Semiconductor contact via structure
    31.
    发明授权
    Semiconductor contact via structure 失效
    半导体接触通孔结构

    公开(公告)号：US5841195A

    公开(公告)日：1998-11-24

    申请号：US448703

    申请日：1995-05-24

    申请人： Yih-Shung Lin ,  Lun-Tseng Lu ,  Fu-Tai Liou ,  Che-Chia Wei ,  John Leonard Walters

    发明人： Yih-Shung Lin ,  Lun-Tseng Lu ,  Fu-Tai Liou ,  Che-Chia Wei ,  John Leonard Walters

    IPC分类号： H01L21/28 ,  H01L21/768 ,  H01L23/485 ,  H01L23/522 ,  H01L23/532

    CPC分类号： H01L23/485 ,  H01L21/76804 ,  H01L2924/0002

    摘要： A method is provided for forming contact via in an integrated circuit. Initially, a first buffer layer is formed over an insulating layer in an integrated circuit. The first buffer layer has a different etch rate from the insulating layer. A second buffer layer is then formed over the first buffer layer, with the second buffer layer having an etch rate which is faster than the first buffer layer. An isotropic etch is performed to create an opening through the second buffer layer and a portion of the first buffer layer. Because the second buffer layer etches faster than the first buffer layer, the slant of the sideswalls of the opening can be controlled. An anisotropic etch is then performed to complete formation of the contact via.

    摘要翻译： 提供了一种用于在集成电路中形成接触通孔的方法。 首先，在集成电路中的绝缘层上形成第一缓冲层。 第一缓冲层具有与绝缘层不同的蚀刻速率。 然后在第一缓冲层上形成第二缓冲层，其中第二缓冲层具有比第一缓冲层快的蚀刻速率。 执行各向同性蚀刻以产生通过第二缓冲层和第一缓冲层的一部分的开口。 因为第二缓冲层比第一缓冲层蚀刻更快，所以可以控制开口的侧壁的倾斜。 然后进行各向异性蚀刻以完成接触通孔的形成。

    Method of making back gate contact for silicon on insulator technology
    32.
    发明授权
    Method of making back gate contact for silicon on insulator technology 失效
    硅绝缘体技术的背栅接触方法

    公开(公告)号：US5610083A

    公开(公告)日：1997-03-11

    申请号：US650697

    申请日：1996-05-20

    申请人： Lap Chan ,  Ravis H. Sundaresan ,  Che-Chia Wei

    发明人： Lap Chan ,  Ravis H. Sundaresan ,  Che-Chia Wei

    IPC分类号： H01L27/12 ,  H01L21/84

    CPC分类号： H01L27/1203

    摘要： A process for creating a back gate contact, in an SOI layer, that can easily be incorporated into a MOSFET fabrication recipe, has been developed. The back gate contact consists of a etched trench, lined with insulator, and filled with doped polysilicon. The polysilicon filled trench electrically connects the semiconductor substrate to overlying metal contacts.

    摘要翻译： 已经开发了用于在SOI层中产生可以容易地并入MOSFET制造配方中的背栅极接触的工艺。 背栅极接触由蚀刻的沟槽组成，内衬绝缘体并填充有多晶硅。 多晶硅填充沟槽将半导体衬底电连接到覆盖的金属触点。

    Interconnect structure for an integrated circuit
    33.
    发明授权
    Interconnect structure for an integrated circuit 失效
    集成电路的互连结构

    公开(公告)号：US5313084A

    公开(公告)日：1994-05-17

    申请号：US891450

    申请日：1992-05-29

    申请人： Che-Chia Wei

    发明人： Che-Chia Wei

    IPC分类号： H01L21/28 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/52 ,  H01L29/540

    CPC分类号： H01L21/76889 ,  H01L21/76895

    摘要： A local interconnect structure for an integrated circuit is formed from a patterned refractory metal silicide. The local interconnect has an overlying oxide layer, which prevents part of the amorphous silicon used to form the interconnect from becoming silicided. This results in a local interconnect layer which has thinner silicide portions than silicide regions formed over adjacent source/drain regions and gate electrodes.

    摘要翻译： 用于集成电路的局部互连结构由图案化的难熔金属硅化物形成。 局部互连具有覆盖的氧化物层，其防止用于形成互连的非晶硅的一部分变成硅化物。 这导致局部互连层，其具有比在相邻源极/漏极区域和栅电极上形成的硅化物区更薄的硅化物部分。

    Method of forming a gate overlap LDD structure
    34.
    发明授权
    Method of forming a gate overlap LDD structure 失效
    形成栅极重叠LDD结构的方法

    公开(公告)号：US5304504A

    公开(公告)日：1994-04-19

    申请号：US71563

    申请日：1993-06-02

    申请人： Che-Chia Wei ,  Ravishankar Sundaresan

    发明人： Che-Chia Wei ,  Ravishankar Sundaresan

    IPC分类号： B01D61/02 ,  B01D61/08 ,  B01D61/12 ,  H01L21/265

    CPC分类号： B01D61/025 ,  B01D61/08 ,  B01D61/12

    摘要： A method is provided for forming a gate overlap LDD structure of an integrated circuit, and an integrated circuit formed according to the same. An oxide layer is formed over a substrate. A four layered gate electrode is formed in an inverse T shape. A first polysilicon layer is formed over the underlying oxide layer. A first conductive layer is formed over the first polysilicon layer. A second polysilicon layer is formed over the first conductive layer. A second conductive layer is then formed over the second polysilicon layer. The second conductive and polysilicon layers are etched to expose a portion of the underlying first conductive layer. Lightly doped drain regions are formed in the substrate adjacent to the second conductive and polysilicon layers. Sidewall oxide spacers are formed on the sides of the second conductive and polysilicon layers and on top of the first conductive layer. The first conductive and polysilicon layers are etched exposing a portion of the underlying oxide layer. Source/drain regions are formed in the substrate adjacent to the first conductive and polysilicon layers.

    摘要翻译： 提供一种用于形成集成电路的栅极重叠LDD结构的方法，以及根据该集成电路形成的集成电路。 在衬底上形成氧化物层。 四层栅电极形成为反T形。 在下面的氧化物层上形成第一多晶硅层。 在第一多晶硅层上形成第一导电层。 在第一导电层上形成第二多晶硅层。 然后在第二多晶硅层上形成第二导电层。 蚀刻第二导电和多晶硅层以暴露下面的第一导电层的一部分。 在与第二导电层和多晶硅层相邻的衬底中形成轻掺杂漏极区。 侧壁氧化物间隔物形成在第二导电层和多晶硅层的侧面上，并且在第一导电层的顶部上。 第一导电和多晶硅层被蚀刻暴露一部分下面的氧化物层。 源极/漏极区域形成在与第一导电层和多晶硅层相邻的衬底中。

    Gate overlapping LDD structure
    35.
    发明授权
    Gate overlapping LDD structure 失效
    门重叠LDD结构

    公开(公告)号：US5276347A

    公开(公告)日：1994-01-04

    申请号：US809398

    申请日：1991-12-18

    申请人： Che-Chia Wei ,  Ravishankar Sundaresan

    发明人： Che-Chia Wei ,  Ravishankar Sundaresan

    IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L29/423 ,  H01L29/78

    CPC分类号： H01L29/6659 ,  H01L21/28061 ,  H01L21/28114 ,  H01L29/42376 ,  H01L29/7836

    摘要： A method is provided for forming a gate overlap LDD structure of an integrated circuit, and an integrated circuit formed according to the same. An oxide layer is formed over a substrate. A four layered gate electrode is formed in an inverse T shape. A first polysilicon layer is formed over the underlying oxide layer. A first conductive layer is formed over the first polysilicon layer. A second polysilicon layer is formed over the first conductive layer. A second conductive layer is then formed over the second polysilicon layer. The second conductive and polysilicon layers are etched to expose a portion of the underlying first conductive layer. Lightly doped drain regions are formed in the substrate adjacent to the second conductive and polysilicon layers. Sidewall oxide spacers are formed on the sides of the second conductive and polysilicon layers and on top of the first conductive layer. The first conductive and polysilicon layers are etched exposing a portion of the underlying oxide layer. Source/drain regions are formed in the substrate adjacent to the first conductive and polysilicon layers.

    摘要翻译： 提供一种用于形成集成电路的栅极重叠LDD结构的方法，以及根据该集成电路形成的集成电路。 在衬底上形成氧化物层。 四层栅电极形成为反T形。 在下面的氧化物层上形成第一多晶硅层。 在第一多晶硅层上形成第一导电层。 在第一导电层上形成第二多晶硅层。 然后在第二多晶硅层上形成第二导电层。 蚀刻第二导电和多晶硅层以暴露下面的第一导电层的一部分。 在与第二导电层和多晶硅层相邻的衬底中形成轻掺杂漏极区。 侧壁氧化物间隔物形成在第二导电层和多晶硅层的侧面上，并且在第一导电层的顶部上。 第一导电和多晶硅层被蚀刻暴露一部分下面的氧化物层。 源极/漏极区域形成在与第一导电层和多晶硅层相邻的衬底中。

    Method of making oxide-isolated source/drain transistor
    37.
    发明授权
    Method of making oxide-isolated source/drain transistor 失效
    制造氧化物隔离源/漏晶体管的方法

    公开(公告)号：US4963502A

    公开(公告)日：1990-10-16

    申请号：US416566

    申请日：1989-10-03

    申请人： Clarence W. Teng ,  Thomas E. Tang ,  Che-Chia Wei

    发明人： Clarence W. Teng ,  Thomas E. Tang ,  Che-Chia Wei

    IPC分类号： H01L21/285 ,  H01L21/336 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08

    CPC分类号： H01L29/66636 ,  H01L21/28525 ,  H01L21/823814 ,  H01L21/823878 ,  H01L29/0638 ,  H01L29/0653 ,  H01L29/0847 ,  H01L27/0921 ,  H01L27/0928

    摘要： A MOS bulk device having source/drain-contact regions 36 which are almost completely isolated by a dielectric 35. These "source/drain" regions 36 are formed by using a silicon etch to form a recess, lining the etched recess with oxide, and backfilling with polysilicon. A short isotropic oxide etch, followed by a polysilicon filament deposition, then makes contact between the oxide-isolated source/drain-contact regions 36 and the channel region 33 of the active device. Outdiffusion through the small area of this contact will form small diffusions 44 in silicon, which act as the electrically effective source/drain regions. Use of sidewall nitride filaments 30 on the gate permits the silicon etch step to be self-aligned.

    摘要翻译： 具有源极/漏极 - 接触区域36的MOS体器件，其几乎完全由电介质35隔离。这些“源极/漏极”区域36通过使用硅蚀刻形成凹部，用氧化物衬在蚀刻的凹槽上，以及 回填多晶硅。 短的各向同性氧化物蚀刻，随后是多晶硅长丝沉积，然后在氧化物隔离的源极/漏极 - 接触区域36和有源器件的沟道区域33之间接触。 通过该接触的小面积的扩散将在硅中形成小的扩散部分44，其作为电有效的源极/漏极区域。 在栅极上使用侧壁氮化物细丝30允许硅蚀刻步骤自对准。

    Definition of anti-fuse cell for programmable gate array application
    40.
    发明授权
    Definition of anti-fuse cell for programmable gate array application 有权
    用于可编程门阵列应用的反熔丝单元的定义

    公开(公告)号：US06307248B1

    公开(公告)日：2001-10-23

    申请号：US09289890

    申请日：1999-04-12

    申请人： Che-Chia Wei ,  Lap Chan ,  Bob Lee ,  Poh Suan Tan

    发明人： Che-Chia Wei ,  Lap Chan ,  Bob Lee ,  Poh Suan Tan

    IPC分类号： H01L2900

    CPC分类号： H01L27/11803 ,  Y10S438/922

    摘要： A method for fabricating an anti-fuse cell using an undoped polysilicon film as a mask in defining the anti-fuse window is described. A layer of silicon oxide is provided over the surface of a semiconductor substrate. A first undoped polysilicon layer is deposited overlying the silicon oxide layer. The first undoped polysilicon layer is covered with a photoresist layer patterned to form a mask. The first undoped polysilicon layer and a portion of the silicon oxide layer are etched away where they are not covered by the mask to form a cell opening. The mask and the remaining silicon oxide within the cell opening are removed. An insulating layer is deposited over the surface of the first undoped polysilicon layer and within the cell opening. A second polysilicon layer is deposited overlying the insulating layer and doped. The second polysilicon layer is patterned to form an anti-fuse cell. Gate electrodes and source and drain regions are formed completing the fabrication of the integrated circuit device.

    摘要翻译： 描述了在限定反熔丝窗口中使用未掺杂的多晶硅膜作为掩模来制造抗熔丝电池的方法。 在半导体衬底的表面上设置一层氧化硅。 第一未掺杂的多晶硅层沉积在氧化硅层上。 第一未掺杂的多晶硅层被图案化以形成掩模的光致抗蚀剂层覆盖。 将第一未掺杂的多晶硅层和一部分氧化硅层蚀刻掉，其中它们不被掩模覆盖以形成电池开口。 除去孔中的掩模和剩余的氧化硅。 绝缘层沉积在第一未掺杂多晶硅层的表面上并且在电池开口内。 第二多晶硅层沉积在绝缘层上并掺杂。 将第二多晶硅层图案化以形成抗熔丝电池。 形成栅电极和源极和漏极区，完成集成电路器件的制造。