公开(公告)号：US06980467B2

公开(公告)日：2005-12-27

申请号：US10314735

申请日：2002-12-09

申请人： Tsu-Jae King

发明人： Tsu-Jae King

IPC分类号： H01L21/265 ,  H01L21/8234 ,  H01L29/423 ,  H01L29/78 ,  G11C7/00

CPC分类号： H01L29/78 ,  H01L21/2652 ,  H01L21/823462 ,  H01L29/42332

摘要： A negative differential resistance (NDR) field-effect transistor element is disclosed, formed on a silicon-based substrate using conventional MOS manufacturing operations. Methods for improving a variety of NDR characteristics for an NDR element, such as peak-to-valley ratio (PVR), NDR onset voltage (VNDR) and related parameters are also disclosed.

公开(公告)号：US06972465B2

公开(公告)日：2005-12-06

申请号：US10760090

申请日：2004-01-15

申请人： Tsu-Jae King ,  David K. Y. Liu

发明人： Tsu-Jae King ,  David K. Y. Liu

IPC分类号： H01L29/78 ,  G11C5/14 ,  G11C11/39 ,  G11C16/04 ,  H01L21/28 ,  H01L21/8238 ,  H01L27/088 ,  H01L27/092 ,  H01L29/66 ,  H01L29/788 ,  H01L29/792 ,  H01L29/72

CPC分类号： B82Y10/00 ,  G11C5/142 ,  G11C11/39 ,  G11C16/04 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/088 ,  H01L29/78 ,  H01L29/788 ,  H01L29/7881 ,  H01L29/792

摘要： A CMOS based n-channel metal-insulator-semiconductor field-effect transistor (MISFET) that exhibits a useful negative differential resistance effect is disclosed. The resulting device can be incorporated into a number of useful applications, including as part of a memory device, a logic device, etc.

摘要翻译： 公开了一种具有有用的负差分电阻效应的基于CMOS的n沟道金属 - 绝缘体 - 半导体场效应晶体管（MISFET）。 所得到的设备可以并入多个有用的应用中，包括作为存储设备的一部分，逻辑设备等。

公开(公告)号：US20050242391A1

公开(公告)日：2005-11-03

申请号：US11120468

申请日：2005-05-02

申请人： Min She ,  Tsu-Jae King

发明人： Min She ,  Tsu-Jae King

IPC分类号： G11C16/04 ,  H01L21/8246 ,  H01L27/115

CPC分类号： H01L27/11568 ,  G11C16/0475 ,  H01L27/115 ,  H01L29/785 ,  Y10S438/954

摘要： Charge migration in a SONOS memory cell is eliminated by physically separating nitride layer storage sites with dielectric material. Increased storage in a cell is realized with a double gate structure for controlling bit storage in line channels between a source and a drain, such as with a FinFET structure in which the gates are folded over the channels on sides of a fin.

摘要翻译： 通过用介电材料物理分离氮化物层存储位置，消除SONOS存储单元中的电荷迁移。 通过双栅极结构来实现电池中的存储增加，用于控制源极和漏极之间的线路通道中的位存储，例如利用FinFET结构，其中栅极折叠在鳍的侧面上的通道上。

公开(公告)号：US20050145955A1

公开(公告)日：2005-07-07

申请号：US11027093

申请日：2004-12-30

申请人： Tsu-Jae King

发明人： Tsu-Jae King

IPC分类号： G11C5/00 ,  G11C11/412 ,  H01L21/336 ,  H01L29/76

CPC分类号： G11C11/4125 ,  G11C5/005

摘要： An active negative differential resistance element (an NDR FET) and a memory device (such as an SRAM) using such elements is disclosed. Soft error rate (SER) performance for NDR FETs and such memory devices are enhanced by adjusting a location of charge traps in a charge trapping layer that is responsible for effectuating an NDR behavior. Both an SER and a switching speed performance characteristic can be tailored by suitable placement of the charge traps.

摘要翻译： 公开了一种使用这种元件的有源负差分电阻元件（NDR FET）和存储器件（例如SRAM）。 NDR FET和这种存储器件的软错误率（SER）性能通过调整负责实现NDR行为的电荷陷阱层中的电荷陷阱的位置来增强。 SER和开关速度性能特性都可以通过充电陷阱的适当放置来定制。

公开(公告)号：US20050128797A1

公开(公告)日：2005-06-16

申请号：US11010132

申请日：2004-12-09

申请人： Tsu-Jae King

发明人： Tsu-Jae King

IPC分类号： G11C11/39 ,  G11C11/412 ,  G11C11/413 ,  G11C11/419 ,  G11C11/00

CPC分类号： G11C11/39 ,  G11C11/413

摘要： An enhanced method of writing and reading a memory device, such as an SRAM using negative differential resistance (NDR) elements), is disclosed. This is done through selective control of biasing of the active elements in a memory cell. For example in a write operation, a memory cell is placed in an intermediate state to increase write speed. In an NDR based embodiments, this is done by reducing a bias voltage to NDR FETs so as to weaken the NDR element (and thus disable an NDR effect) during the write operation. Conversely, during a read operation, the bias voltages are increased to enhance peak current (as well as an NDR effect), and thus provide additional current drive to a BIT line. Embodiments using such procedures achieve superior peak to valley current ratios (PVR), read/write speed, etc.

公开(公告)号：US06864104B2

公开(公告)日：2005-03-08

申请号：US10215137

申请日：2002-08-08

申请人： Tsu-Jae King

发明人： Tsu-Jae King

IPC分类号： G11C11/40 ,  H01L21/00

CPC分类号： G11C11/40 ,  G11C2211/5614

摘要： A silicon-on-insulator (SOI) memory device (such as an SRAM) using negative differential resistance (NDR) elements is disclosed. Body effect performances for NDR FETs (and other FETs) that may be used in such device are enhanced by floating a body of some/all the NDR FETs.

摘要翻译： 公开了使用负差分电阻（NDR）元件的绝缘体上硅（SOI）存储器件（例如SRAM）。 通过漂浮一些/全部NDR FET来增强可用于这种器件的NDR FET（和其他FET）的体效应性能。

公开(公告)号：US06794234B2

公开(公告)日：2004-09-21

申请号：US10315476

申请日：2002-12-09

申请人： Igor Polishchuk ,  Pushkar Ranade ,  Tsu-Jae King ,  Chenming Hu

发明人： Igor Polishchuk ,  Pushkar Ranade ,  Tsu-Jae King ,  Chenming Hu

IPC分类号： H01L218238

CPC分类号： H01L21/28079 ,  H01L21/823842 ,  H01L29/4958

摘要： A gate structure for a MOSFET device comprises a gate insulation layer, a first layer of a first metal abutting the gate insulation layer, and a second layer overlying the first layer and comprising a mixture of the metal of the first layer and a second metal, the metal layers formed by the diffusion of the first metal into and through the second metal. The second metal can be used as the gate for a n-MOS transistor, and the mixture of first metal and second metal overlying a layer of the first metal can be used as a gate for a p-MOS transistor where the first metal has a work function of about 5.2 eV and the second metal has a work function of about 4.1 eV.

公开(公告)号：US06596617B1

公开(公告)日：2003-07-22

申请号：US09602658

申请日：2000-06-22

申请人： Tsu-Jae King ,  David K.Y. Liu

发明人： Tsu-Jae King ,  David K.Y. Liu

IPC分类号： H01L2128

CPC分类号： H01L29/7881 ,  G11C5/142 ,  H01L29/788 ,  H01L29/792

摘要： A method of making an n-channel metal-insulator-semiconductor field-effect transistor (MISFET) that exhibits negative differential resistance in its output characteristic (drain current as a function of drain voltage) is disclosed. By implanting ions into a substrate that is later thermally oxidized, a number of temporary charge trapping sites can be established above a channel region of a transistor. The channel is also heavily doped, so that a strong electrical field can be generated to accelerate hot carriers into the temporary charge trapping sites. The insulating layer formed during the oxidation step is made sufficiently thick to prevent quantum tunnelingo of the hot carriers into a gate electrode. Other suitable and conventional processing steps are used to finalize completion of the fabrication of the NDR device so that the entire process is compatible and achieved with CMOS processing techniques.

摘要翻译： 公开了一种制造在其输出特性（作为漏极电压的函数的漏极电流）中呈现负的差分电阻的n沟道金属 - 绝缘体 - 半导体场效应晶体管（MISFET）的方法。 通过将离子注入到稍后被热氧化的衬底中，可以在晶体管的沟道区上方建立许多临时电荷捕获位点。 该通道也是重掺杂的，因此可以产生强电场以将热载流子加速到临时电荷捕获位置。 在氧化步骤期间形成的绝缘层足够厚以防止热载流子的量子隧穿进入栅电极。 使用其它合适的和常规的处理步骤来完成NDR设备的制造完成，使得整个过程与CMOS处理技术相兼容并实现。

公开(公告)号：US06512274B1

公开(公告)日：2003-01-28

申请号：US09603101

申请日：2000-06-22

申请人： Tsu-Jae King ,  David K. Y. Liu

发明人： Tsu-Jae King ,  David K. Y. Liu

IPC分类号： H01L2902

CPC分类号： B82Y10/00 ,  G11C5/142 ,  G11C11/39 ,  G11C16/04 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/088 ,  H01L29/78 ,  H01L29/788 ,  H01L29/7881 ,  H01L29/792

摘要： An n-channel metal-insulator-semiconductor field-effect transistor (MISFET) that exhibits negative differential resistance in its output characteristic (drain current as a function of drain voltage) is disclosed. For a fixed gate voltage, the MISFET channel current, which flows between the drain and source terminals of the transistor, firstly increases as the drain-to-source voltage increases above zero Volts. Once the drain-to-source voltage reaches a pre-determined level, the current subsequently decreases with increasing drain-to-source voltage. In this region of operation, the device exhibits negative differential resistance, as the drain current decreases with increasing drain voltage. The drain-to-source voltage corresponding to the onset of negative differential resistance is also tunable. In addition, the drain current and negative differential resistance can be electronically tailored by adjusting the gate voltage. The resulting device can be incorporated into a number of useful applications, including as part of a memory device, a logic device, etc.

摘要翻译： 公开了在其输出特性（作为漏极电压的函数的漏极电流）中呈现负的差分电阻的n沟道金属 - 绝缘体 - 半导体场效应晶体管（MISFET）。 对于固定栅极电压，在晶体管的漏极和源极端子之间流动的MISFET沟道电流首先随着漏极 - 源极电压增加到零伏特而增加。 一旦漏极到源极电压达到预定电平，电流随着漏极 - 源极电压的增加而减小。 在该操作区域中，随着漏极电压的增加，漏极电流降低，器件呈现负的差分电阻。 对应于负差分电阻开始的漏极 - 源极电压也是可调谐的。 此外，漏电流和负差分电阻可以通过调整栅极电压进行电子定制。 所得到的设备可以并入多个有用的应用中，包括作为存储设备的一部分，逻辑设备等。

公开(公告)号：US5707744A

公开(公告)日：1998-01-13

申请号：US578810

申请日：1995-12-26

申请人： Tsu-Jae King ,  Jackson H. Ho

发明人： Tsu-Jae King ,  Jackson H. Ho

IPC分类号： H01L21/20 ,  B32B17/06

CPC分类号： H01L21/2022

摘要： A new polycrystalline silicon film which has been crystallized using a polycrystalline silicon-germanium (poly-Si.sub.1-x Ge.sub.x) capping film to "seed" crystallization of an amorphous silicon film on an upper surface of a substrate. The polycrystalline silicon film has no nucleation sites and a greater number of grain boundaries in the region near the polycrystalline silicon upper surface than in the region near the polycrystalline silicon and substrate upper surface interface. This indicates that crystallization and crystal growth occurred from the polycrystalline silicon upper surface and proceeded in a direction towards the substrate upper surface.

摘要翻译： 已经使用多晶硅锗（poly-Si1-xGex）覆盖膜结晶的新型多晶硅膜，以在基板的上表面“籽晶化”非晶硅膜。 多晶硅膜在多晶硅上表面附近的区域中不具有多晶硅和衬底上表面界面附近的区域中的成核位点和更多的晶界。 这表明结晶和晶体生长从多晶硅上表面发生并且朝向衬底上表面的方向进行。